Table of Contents

• PolyMiR: Polynomial Formal Verification of the MicroRV32 ProcessorLennart Weingarten, Kamalika Datta, Rolf Drechsler. [doi]
• Low power Circuit Design Using Dynamic GDI Technique in CNTFET TechnologyAmandeep Singh Rehal. [doi]
• Experimental Verification of Uncoupled Memristive Cellular Nonlinear Network by Processing the EDGE Detection TaskYongmin Wang, Kristoffer Schnieders, Vasileios G. Ntinas, Alon Ascoli, Felix Cüppers, Susanne Hoffmann-Eifert, Stefan Wiefels, Ronald Tetzlaff, Vikas Rana, Stephan Menzel. [doi]
• A T-depth two Toffoli gate for 2D square lattice architecturesAlexandru Paler, Evan E. Dobbs, Joseph S. Friedman. [doi]
• Electrical Properties of Proteinoids for Unconventional Computing ArchitecturesPanagiotis Mougkogiannis, Andrew Adamatzky. [doi]
• Concept paper on novel radio frequency resistive switchesAsal Kiazadeh, Jonas Deuermeier, Emanuel Carlos, Rodrigo Martins, Sérgio Matos, Fabio Martinho Cardoso, Luis Manuel Pessoa. [doi]
• VLCP: A High-Performance FPGA-based CNN Accelerator with Vector-level Cluster PruningShuo Ran, Bi-Wu, Ke Chen 0018, Weiqiang Liu 0001. [doi]
• Spin Wave Threshold Logic GatesArne Van Zegbroeck, Pantazis Anagnostou, Said Hamdioui, Christoph Adelmann, Florin Ciubotaru, Sorin Cotofana. [doi]
• LUT-based RRAM Model for Neural Accelerator Circuit SimulationMax Uhlmann, Tommaso Rizzi, Jianan Wen, Emilio Pérez-Bosch Quesada, Bakr Al Beattie, Karlheinz Ochs, Eduardo Pérez, Philip Ostrovskyy, Corrado Carta, Christian Wenger, Gerhard Kahmen. [doi]
• A Behavioural Compact Model for Programmable Neuromorphic ReRAMMohamad Moner Al Chawa, Ronald Tetzlaff, Christos Tjortjis, Stavros G. Stavrinides, Carol de Benito, Rodrigo Picos. [doi]
• A Spatial-Designed Computing-In-Memory Architecture Based on Monolithic 3D Integration for High-Performance SystemsJiaming Li, Bin Gao, Ruihua Yu, Peng Yao, Jianshi Tang, He Qian, Huaqiang Wu. [doi]
• Exploring Multi-Valued Logic and its Application in Emerging Post-CMOS TechnologiesSimranjeet Singh, Elmira Moussavi, Christopher Bengel, Sachin B. Patkar, Rainer Waser, Rainer Leupers, Vikas Rana, Vivek Pachauri, Stephan Menzel, Farhad Merchant. [doi]
• Accurate and Energy-Efficient Stochastic Computing with Van Der Corput SequencesMehran Shoushtari Moghadam, Sercan Aygun, Mohsen Riahi Alam, Jonas I Schmidt, M. Hassan Najafi, Nima Taherinejad. [doi]
• Towards Faster Reinforcement Learning of Quantum Circuit Optimisation: Exponential Reward FunctionsIoana Moflic, Alexandru Paler. [doi]
• Robust Ex-situ Training of Memristor Crossbar-based Neural Network with Limited Precision WeightsRaqibul Hasan. [doi]
• On-Chip Optimization and Deep Reinforcement Learning in Memristor Based ComputingMd. Shahanur Alam, Chris Yakopcic, Tarek M. Taha. [doi]
• Heterogeneous Instruction Set Architecture for RRAM-enabled In-memory ComputingHouji Zhou, Zhiwei Zhou, Shengguang Ren, Jia Chen, Yi Li, Xiangshui Miao. [doi]
• Minimal Design of SiDB Gates: An Optimal Basis for Circuits Based on Silicon Dangling BondsJan Drewniok, Marcel Walter, Robert Wille. [doi]
• Hyper Dimensional Computing with Ferroelectric Tunneling JunctionsStefan Slesazeck, Suzanne Lancaster, John Reuben, Shima Hosseinzadeh, Dietmar Fey, Thomas Mikolajick. [doi]
• A Robust Time-based Error-Proofing Readout Scheme for MRAMQianlei Ou, Shixing Li, Chao Wang, He Zhang, Zhaohao Wang. [doi]
• Single Electron Shuttling between N-Donor and Si/SiO2 Interface at Room TemperatureSoumya Chakraborty, Arup Samanta. [doi]
• Reducing the Complexity of Operational Domain Computation in Silicon Dangling Bond LogicMarcel Walter, Jan Drewniok, Samuel Sze Hang Ng, Konrad Walus, Robert Wille. [doi]
• Impact of the switching mode on the read noise of ReRAM devicesKristoffer Schnieders, Stephan Aussen, Felix Cüppers, Susanne Hoffmann-Eifert, Stefan Wiefels. [doi]
• Non-idealities and Design Solutions for Analog Memristor-Based Content-Addressable MemoriesPaul-Philipp Manea, Chirag Sudarshan, Felix Cüppers, John Paul Strachan. [doi]
• Non Volatile Operators Emulation PlatformAlban Nicolas, Cédric Marchand 0002, David Navarro. [doi]
• A Reconfigurable and Machine Learning attack resistant strong PUF based on Arbiter Mechanism and SOT-MRAMPengbin Li, Zhengyi Hou, Hanran Gao, Bi Wang, Zhaohao Wang. [doi]
• Neural Network Modeling Bias for Hafnia-based FeFETsOsama Yousuf, Imtiaz Hossen, Andreu Glasmann, Sina Najmaei, Gina C. Adam. [doi]
• An RRAM-based PUF with Adjustable Programmable Voltage and Multi-Mode OperationYijun Cui, Jiang Li, Chongyan Gu, Chenghua Wang, Weiqiang Liu 0001. [doi]
• Stochastic template in cellular nonlinear networks modeling memristor induced synaptic noiseDimitrios Prousalis, Vasileios G. Ntinas, Ioannis Messaris, Ahmet Samil Demirkol, Alon Ascoli, Ronald Tetzlaff. [doi]
• Post-Layout Optimization for Field-coupled NanotechnologiesSimon Toni Hofmann, Marcel Walter, Robert Wille. [doi]
• Towards Temporal Information Processing - Printed Neuromorphic Circuits with Learnable FiltersHaibin Zhao, Priyanjana Pal, Michael Hefenbrock, Michael Beigl, Mehdi Baradaran Tahoori. [doi]
• Enhanced Switching in Solid Polymer Electrolyte Memristor Devices via the addition of Interfacial Barriers and Quantum DotsMichael Gater, Ali M. Adawi, Neil T. Kemp. [doi]
• Multiplexer Optimization for Adders in Stochastic ComputingSercan Aygun, M. Hassan Najafi, Lida Kouhalvandi, Ece Olcay Günes. [doi]
• Optically Controlled Memristor Using Hybrid ZnO Nanorod/Polymer MaterialAyoub H. Jaafar, Neil T. Kemp. [doi]
• Resilience and Precision Assessment of Natural Language Processing Algorithms in Analog In-Memory Computing: A Hardware-Aware StudyAmirhossein Parvaresh, Shima Hosseinzadeh, Dietmar Fey. [doi]
• Memristor-based Network Switching Architecture for Energy Efficient Cognitive Computational ModelsSaad Saleh, Boris Koldehofe. [doi]
• Material and Physical Reservoir Computing for Beyond CMOS Electronics: Quo Vadis?Christof Teuscher. [doi]