Table of Contents

• Bridging the gap between design and simulation of low voltage CMOS circuitsCristina Missel Adornes, Deni Germano Alves Neto, Márcio Cherem Schneider, Carlos Galup-Montoro. 1-5 [doi]
• An LO Frequency Tripler with Phase Shifter and Detector in 28nm FD-SOI CMOS for 28-GHz TransceiversRikard Gannedahl, Henrik Sjöland. 1-7 [doi]
• A 0.8-V, 2.88-GHz Double-Tail Latched Comparator in 22-nm FDSOI CMOS TechnologyHarshitha Basavaraju, David Borggreve, Enno Böhme, Frank Vanselow, Erkan Nevzat Isa, Linus Maurer. 1-6 [doi]
• Approximate Feature Extraction for Low Power Epileptic Seizure Prediction in Wearable DevicesZain Taufique, Anil Kanduri, Muhammad Awais Bin Altaf, Pasi Liljeberg. 1-7 [doi]
• High-Level Synthesis Implementation of an Accurate HEVC Interpolation Filter on an FPGAPanu Sjövall, Matti Rasinen, Ari Lemmetti, Jarno Vanne. 1-7 [doi]
• Signal Integrity in High Speed 3D IC Design- A Case StudyShadi M. Harb, William R. Eisenstadt. 1-5 [doi]
• CMOS inverter linearization technique with active source degenerationLuis Henrique Rodovalho, Cesar Ramos Rodrigues, Orazio Aiello. 1-6 [doi]
• Powerline Communication System-on-Chip in 180 nm Harsh Environment SOI TechnologyTobias Stuckenberg, Malte Rücker, Niklas Rother, Rochus Nowosielski, Frank Wiese, Holger Blume. 1-5 [doi]
• Low-Complexity Unidimensional CNN based Brain Speller for Embedded PlatformsGiovanni Mezzina, Daniela De Venuto. 1-6 [doi]
• A digital switching scheme to reduce DAC glitches using code-dependent randomizationOscar Morales Chacon, J. Jacob Wikner, Atila Alvandpour, Liter Siek. 1-5 [doi]
• Low-Voltage Energy Efficient Neural Inference by Leveraging Fault Detection TechniquesMehdi Safarpour, Tommy Z. Deng, John Massingham, Lei Xun, Mohammad Sabokrou, Olli Silvén. 1-5 [doi]
• Broadband Analog Predistortion Circuits Utilizing Derivative SuperpositionSauli Haukka, Jere Rusanen, Alok Sethi, Aarno Pärssinen, Timo Rahkonen, Janne P. Aikio. 1-5 [doi]
• A 7.2µW Magnitude/Phase Bio-impedance Measurement Front-End with PWM Output in 0.18µm CMOSMilad Zamani, Yasser Rezaeiyan, Omid Shoaei, Farshad Moradi. 1-5 [doi]
• Intelligent Cognitive Radio Architecture Applying Machine Learning and ReconfigurabilityJari Nurmi, Darshika G. Perera. 1-6 [doi]
• An architecture for ultra-low-voltage ultra-low-power compressed sensing-based acquisition systemsCarmine Paolino, Fabio Pareschi, Mauro Mangia, Riccardo Rovatti, Gianluca Setti. 1-7 [doi]
• Approximate Computation on Commodity Computers through Bit-Serial ProcessingChuanjun Zhang, Shivangi Katiyar, Mitch Diamond, Olivier Franza. 1-7 [doi]
• RTL Delay Prediction Using Neural NetworksDaniela Sanchez Lopera, Lorenzo Servadei, Vishwa Priyanka Kasi, Sebastian Siegfried Prebeck, Wolfgang Ecker. 1-7 [doi]
• Subthreshold Power PC and Nand Race-Free Flip-Flops in Frequency Divider ApplicationsSomayeh Hossein Zadeh, Trond Ytterdal, Snorre Aunet. 1-6 [doi]
• Accelerator Interface for PatmosClemens Pircher, Alexander Baranyai, Christoph Lehr, Martin Schoeberl. 1-7 [doi]
• A Gate Voltage Sensing Ripple Reduction Control Technique for Switched-Capacitor DC-DC ConvertersChristian Westmark Sønnichsen, Paul Stephansson. 1-7 [doi]
• Design of Low Power VLSI Architecture for Classification of Arrhythmic Beats Using DNN for Wearable Device ApplicationsMeenali Janveja, Mayank Tantuway, Ketan Chaudhari, Gaurav Trivedi. 1-6 [doi]
• Clock Tree Generation by Abutment in Synchoros VLSI DesignDimitrios Stathis 0001, Panagiotis Chaourani, Syed M. A. H. Jafri, Ahmed Hemani. 1-7 [doi]
• A 25.6-27.5GHz Phase-Locked Loop for SerDes Transceiver Clocking in 5nm FinFETPing Lu. 1-4 [doi]
• LOCAL: Low-Complex Mapping Algorithm for Spatial DNN AcceleratorsMidia Reshadi, David Gregg. 1-7 [doi]
• Low Power CMOS Thyristor-Based Relaxation Oscillator with Efficient Current CompensationMarcel Jotschke, Gokulkumar Palanisamy, Wilmar Carvajal Ossa, Harsha Prabakaran, Jeongwook Koh, Matthias Kuhl, Wolfgang H. Krautschneider, Torsten Reich, Christian Mayr. 1-5 [doi]
• Machine Learning Approach for Accelerating Simulation-based Fault InjectionLi Lu, Junchao Chen, Anselm Breitenreiter, Oliver Schrape, Markus Ulbricht 0002, Milos Krstic. 1-6 [doi]
• Unified OpenCL Integration Methodology for FPGA DesignsTopi Leppänen, Panagiotis Mousouliotis, Georgios Keramidas, Joonas Multanen, Pekka Jääskeläinen. 1-7 [doi]
• A Two-Stage Single-Ended OTA with Improved Composite TransistorsLuis Henrique Rodovalho, Cesar Ramos Rodrigues, Orazio Aiello. 1-7 [doi]
• ChiselVerify: An Open-Source Hardware Verification Library for Chisel and ScalaAndrew Dobis, Tjark Petersen, Hans Jakob Damsgaard, Kasper Juul Hesse Rasmussen, Enrico Tolotto, Simon Thye Andersen, Richard Lin, Martin Schoeberl. 1-7 [doi]
• A Methodology for Automated Mining of Compact and Accurate Assertion SetsMohammad Reza Heidari Iman, Jaan Raik, Maksim Jenihhin, Gert Jervan, Tara Ghasempouri. 1-7 [doi]
• Linearity Boosting Technique with Adaptive Sampling Switch Assisted by Signal Prediction for Multi-Channel ADCs in Standard CMOS ProcessZihao Jiao, Xiaofei Wang, Hongrui Luo, Jie Zhang 0039, Ruizhi Zhang 0002, Hong Zhang 0009. 1-5 [doi]
• Analysis and Design of Start-up Circuits for a 48 V-12 V Switched-Capacitor Converter in a 180 nm SOI ProcessMarkus Mogensen Henriksen, Dennis Øland Larsen, Pere Llimós Muntal. 1-7 [doi]