Table of Contents

• A low-noise high-linear wide dynamic-range MTJ-based magnetic field sensorYasser Rezaeiyan, Nikolaj Lykkeberg Madsen, Tim Böhnert, Milad Zamani, Sonal Shreya, Elvira Paz, Hooman Farkhani, Ricardo Ferreira 0003, Farshad Moradi. 1-4 [doi]
• Co-Simulating Region-Based Dynamic Voltage Scaling for FPGA Architecture DesignJohannes Pfau, Jiro Hernandez, Maximilian Reuter, Klaus Hofmann, Jürgen Becker 0001. 1-7 [doi]
• Design of a Dual-Band Wireless Power and Data Transfer Coil for Multisite Biomedical ImplantsMohammad Javad Karimi, Junyan Qian, Catherine Dehollain, Alexandre Schmid. 1-6 [doi]
• Guidelines for Implementing Control Flow Checking into Automotive Embedded Applications Developed with C LanguageJacopo Sini, Mohammadreza Amel Solouki, Massimo Violante. 1-6 [doi]
• Transitioning to Chisel in University Education: Experiences and Lessons LearnedLuca Pezzarossa, Martin Schoeberl. 1-7 [doi]
• Performance Modelling of Optimal Combination Algorithms Applied to Arbitrary Data Converter ArchitecturesFrancesco Gagliardi 0002, Danilo Scintu, Massimo Piotto, Paolo Bruschi, Michele Dei. 1-7 [doi]
• Approximation-aware Task Partitioning on an Approximate-Exact MPSoC (AxE)Sini Huemer, Ahmad Sadigh Baroughi, Hadi Shahriar Shahhoseini, Nima Taherinejad. 1-7 [doi]
• Deep Learning-Enhanced Parameter Extraction for Equivalent Circuit Modeling in Electrochemical Impedance SpectroscopyQirui Hua, Ming Shen 0001. 1-6 [doi]
• A complete SHA-3 hardware library based on a high efficiency Keccak designEros Camacho-Ruiz, Santiago Sánchez-Solano, Macarena C. Martínez-Rodríguez, Piedad Brox. 1-7 [doi]
• Active Noise Cancelling Method for An Electro-Optical Detection SystemRuixing Yang, Yingge Chen, François Ladouceur, Nigel H. Lovell, Amr Al Abed, Torsten Lehmann. 1-7 [doi]
• A mm-Wave Differential-to-Quadrature Frequency Tripler with Automatic Locking and Quadrature CorrectionRikard Gannedahl, Henrik Sjöland. 1-6 [doi]
• FPGA Implementation of MLP, 1D-CNN and TTTratio algorithms for Neutron/Gamma-ray Discrimination using Plastic ScintillatorAli Hachem, Imane Belalchheb, Yoann Moline, Frédérick Carrel, Gwenolé Corre. 1-7 [doi]
• Analysing Mismatch effect of CMOS Neurons in Spiking Neural Network with Winner-take-all MechanismSahibia Kaur Vohra, Alex P. James, Mahendra Sakare, Devarshi Mrinal Das. 1-7 [doi]
• Analyzing Step-Size Approximation for Fixed-Point Implementation of LMS and BLMS AlgorithmsMohd. Tasleem Khan, Oscar Gustafsson. 1-5 [doi]
• An IMPLY-based Semi-Serial Approximate In-Memristor AdderFabian Seiler, Nima Taherinejad. 1-7 [doi]
• Reliable Code-Based Post-Quantum Cryptographic Algorithms through Fault Detection on FPGAAlvaro Cintas Canto, Mehran Mozaffari Kermani, Reza Azarderakhsh. 1-5 [doi]
• Control Plane Isolation of Network Security Protocols using FPGA-SoC Trusted Execution EnvironmentDaniel Dik, Michael Stübert Berger. 1-6 [doi]
• Performance Evaluation of PicoRV32 RISC-V Softcore for Resource-Constrained DevicesMarek Jahnke, Lucas Bublitz, Ulf Kulau. 1-6 [doi]
• Adaptive Lock-Step System for Resilient Multiprocessing ArchitecturesJunchao Chen 0001, Li Lu, Marko S. Andjelkovic, Markus Ulbricht 0002, Milos Krstic. 1-6 [doi]
• Evaluation of Power-of-two Quantization for Multiplier-less Near-Memory and In-Memory Computing Schemes for Biomedical ApplicationsAntoine Gautier 0003, Benoît Larras, Olev Märtens, Deepu John, Antoine Frappé. 1-5 [doi]
• Preliminary Performance and Memory Access Scalability Study of Thick Control Flow ProcessorsMartti Forsell, Jussi Roivainen, Ville Leppänen, Jesper Larsson Träff. 1-7 [doi]
• Active Wideband 55-100-GHz Downconversion Mixer in 22-nm FDSOI CMOSKimi Jokiniemi, Kaisa Ryynänen, Joni Vähä, Elmo Kankkunen, Kari Stadius, Jussi Ryynänen. 1-7 [doi]
• Compensating Quadrature Hybrid Mismatch Effects in Integrated Balanced Power AmplifierJere Rusanen, Negar Shabanzadeh, Aarno Pärssinen, Timo Rahkonen, Janne P. Aikio. 1-5 [doi]
• SyncRim - A modern Simulator for Synchronous Circuits implemented in RustPawel Dzialo, Erik Vd. Boom, Per Lindgren. 1-6 [doi]
• Memory Mapped I/O Register Test Case Generator for Large Systems-on-ChipRoni Hämäläinen, Henri Lunnikivi, Timo Hämäläinen 0001. 1-7 [doi]
• High-level FPGA Design of Deep Learning Hyperspectral Anomaly DetectionSamuel Boyle, Aksel Gunderson, Milica Orlandic. 1-5 [doi]
• neuroAIx: FPGA Cluster for Reproducible and Accelerated Neuroscience Simulations of SNNsKevin Kauth, Tim Stadtmann, Vida Sobhani, Tobias Gemmeke. 1-7 [doi]
• Effective Processor Model Generation from Instruction Set Simulator to Hardware DesignJohannes Kappes, Robert Kunzelmann, Karsten Emrich, Conrad Foik, Daniel Mueller-Gritschneder, Wolfgang Ecker. 1-7 [doi]
• Cell-Based Aging Sensor Using Built-In Speed GradingOnt-Derh Lin, Shi-Yu Huang. 1-6 [doi]
• High-Performance Floating Resistor-based Ring Amplifier for Switched Capacitor CircuitsManish Pundir, Bipul Kumar Singh, Ninad Bandu Kamble, Ambika Prasad Shah. 1-6 [doi]
• A Low-Power Current-Reuse Self-Biased Regulated-Cascode TIA in 130nm SiGe BiCMOS for Low-Noise and High Data Rate ApplicationsBehnam Abdollahi, Horst Zimmermann. 1-7 [doi]
• AFOCL: Portable OpenCL Programming of FPGAs via Automated Built-in Kernel ManagementTopi Leppänen, Joonas Multanen, Leevi Leppänen, Pekka Jääskeläinen. 1-7 [doi]
• Streaming Matrix Transposition on FPGAs Using Distributed MemoriesMikael Henriksson, Oscar Gustafsson. 1-6 [doi]
• Time-varying distortion contribution analysis of single-transistor mixersNegar Shabanzadeh, Aarno Pärssinen, Timo Rahkonen. 1-5 [doi]
• Toward All-Digital Time-Domain Neural Network Accelerators for In-Sensor Processing ApplicationsAhmed M. Mohey, Marko Kosunen, Jussi Ryynänen, Martin Andraud. 1-6 [doi]
• Verification of Approximate Hardware Designs with ChiselVerifyHans Jakob Damsgaard, Aleksandr Ometov, Jari Nurmi. 1-7 [doi]
• Tailored AVX2 Transform Kernels for Versatile Video CodingKari Siivonen, Joose Sainio, Alexandre Mercat, Jarno Vanne. 1-6 [doi]
• A 1.4 GS/s TI Pipelined-SAR analog-to-digital converter in 22-nm FDSOI CMOSHamid Karrari, Pietro Andreani, Siyu Tan. 1-5 [doi]
• Ultra Low Power ASK Demodulator/Manchester Decoder for Biomedical ApplicationsWei Cao, Alireza Saberkari, Atila Alvandpour. 1-4 [doi]
• An Open-Source Micro-Watt 130-dB Delta-Sigma Modulator with 600mVpp Input Range for DC-Coupled Biosignal AcquisitionMichael Köfinger, Patrick Fath, Harald Pretl. 1-6 [doi]
• A First Experimental Study of Fixed-Point Approximate Arithmetic in Recursive Lattice FiltersPeter Koch 0001, Yannick Le Moullec. 1-6 [doi]
• Low Power LDPC Decoding by Reliable Voltage Down-ScalingJoonas Valkama, Mehdi Safarpour, Håkan Dicander, Zhongmin Deng, Andreas Burg, Olli Silvén. 1-5 [doi]
• A 370-nW Quad-Channel Multi-Mode Bio-Signal Acquisition AFE with 2.9-µVrms Input NoisePatrick Fath, Harald Pretl. 1-5 [doi]
• Tydi-Chisel: Collaborative and Interface-Driven Data-Streaming AcceleratorsCasper Cromjongh, Yongding Tian, H. Peter Hofstee, Zaid Al-Ars. 1-7 [doi]
• Enhancing Robustness and Reliability of Networks-on-Chip with Network CodingJulian Haase, Sebastian Jaster, Elke Franz 0001, Diana Göhringer. 1-7 [doi]
• Automated Replacement of State-Holding Flip-Flops to Enable Non-Volatile CheckpointingFabian Kreß, Johannes Pfau, Fabian Kempf, Patrick Schmidt, Zhuofan He, Tanja Harbaum, Jürgen Becker 0001. 1-7 [doi]
• Implementation and Performance of a General Purpose Incremental Sigma-Delta ConverterOlle Martinsson. 1-6 [doi]
• An Automated EM-Simulation Environment with Parameterized Layout Generation for Microwave Integrated CircuitsKaisa Ryynänen, Veeti Lahtinen, Santeri Porrasmaa, Kari Stadius, Marko Kosunen, Jussi Ryynänen. 1-6 [doi]
• Lens Flare Attenuation Accelerator Design with Deep Learning and High-Level SynthesisDavid Fosca Gamarra, Per Gunnar Kjeldsberg, Henrik Sundbeck. 1-7 [doi]