Abstract is missing.
- (System)Verilog to Chisel Translation for Faster Hardware DesignJean Bruant, Pierre-Henri Horrein, Olivier Muller, Tristan Groléat, Frédéric Pétrot. 1-7 [doi]
- Mathematic models based on multiple-criteria decision analysis for tuning industrial CNN in an FPGA computing clusterChen Wu, Virginie Fresse, Benoît Suffran, Hubert Konik. 1-7 [doi]
- NestedNet: A Container-based Prototyping Tool for Hierarchical Software Defined NetworksXuzhi Zhang, Narendra Prabhu, Russell Tessier. 1-7 [doi]
- A combined fast/cycle accurate simulation tool for reconfigurable accelerator evaluation: application to distributed data managementErwan Lenormand, Thierry Goubier, Loïc Cudennec, Henri-Pierre Charles. 1-7 [doi]
- Advanced Debugging Architecture for Smart Inertial Sensors using Sensor-in-the-LoopDaniel Gis, Nils Büscher, Christian Haubelt. 1-7 [doi]
- FPGA based design and prototyping of efficient 5G QC-LDPC channel decodingJérémy Nadal, Amer Baghdadi. 1-7 [doi]
- MPSoC Fast Prototyping of a Reconfigurable DU Downlink Transmission Chain for 5G New RadioJosé Domingues, Fábio D. L. Coutinho, Pedro M. C. Marques, Samuel S. Pereira, Hugerles S. Silva, Arnaldo S. R. Oliveira. 1-7 [doi]
- Desired Footprint by Technology Mapping Modification using a Genetic Algorithm in Odin IISeyed Alireza Damghani, Jean-Philippe Legault, Kenneth B. Kent. 1-7 [doi]
- Hardware-in-the-loop simulation with dynamic partial FPGA reconfiguration applied to computer vision in ROS-based UAVErwan Moréac, El Mehdi Abdali, François Berry, Dominique Heller, Jean-Philippe Diguet. 1-7 [doi]