Abstract is missing.
- FPGA Prototyping of Systolic Array-based Accelerator for Low-Precision Inference of Deep Neural NetworksSoobeom Kim, Seunghwan Cho, Eunhyeok Park, Sungjoo Yoo. 1-7 [doi]
- An FPGA-based Emulation Platform for Edge Computing Node Design ExplorationTheo Soriano, David Novo, Pascal Benoit. 8-14 [doi]
- Prototyping FPGA through overlaysThéotime Bollengier, Loïc Lagadec, Ciprian Teodorov. 15-21 [doi]
- Data Augmentation Framework for Smart Sensor System Development Using the Sensor-in-the-Loop Prototyping PlatformNils Büscher, Daniel Gis, Johann-Peter Wolff, Christian Haubelt. 22-28 [doi]
- Template-Driven and Hardware-Centric Cross-Domain E/E Architecture SimulationKevin Neubauer, Leonard Masing, Michael Mahl, Jürgen Becker 0001, Max E. Kramer, Clemens Reichmann. 29-35 [doi]
- Implementing Rowhammer Memory Corruption in the gem5 SimulatorLoïc France, Florent Bruguier, Maria Mushtaq, David Novo, Pascal Benoit. 36-42 [doi]
- Instruction Set Design Methodology for In-Memory Computing through QEMU-based System EmulatorKevin Mambu, Henri-Pierre Charles, Julie Dumas, Maha Kooli. 43-49 [doi]
- HyCo: A Low-Latency Hybrid Control Plane for Optical Interconnection NetworksFelipe Göhring de Magalhães, Mahdi Nikdast, Fabiano Hessel, Odile Liboiron-Ladouceur, Gabriela Nicolescu. 50-56 [doi]
- Heterogeneous Logic Implementation for Adders in VTRHarpreet Kaur, Georgiy Krylov, Seyed Alireza Damghani, Kenneth B. Kent. 57-63 [doi]
- Integrating Quick Resource Estimators in Hardware Construction Framework for Design Space ExplorationBruno Ferres, Olivier Muller, Frédéric Rousseau 0001. 64-70 [doi]