Abstract is missing.
- How sensitive is processor customization to the workload's input datasets?Maximilien Breughe, Zheng Li, Yang Chen, Stijn Eyerman, Olivier Temam, Chengyong Wu, Lieven Eeckhout. 1-7 [doi]
- TARCAD: A template architecture for reconfigurable accelerator designsMuhammad Shafiq, Miquel Pericàs, Nacho Navarro, Eduard Ayguadé. 8-15 [doi]
- Customized MPSoC synthesis for task sequenceLiang Chen, Nicolas Boichat, Tulika Mitra. 16-21 [doi]
- Integrating formal verification and high-level processor pipeline synthesisEriko Nurvitadhi, James C. Hoe, Timothy Kam, Shih-Lien Lu. 22-29 [doi]
- USHA: Unified software and hardware architecture for video decodingAdarsha Rao, S. K. Nandy, Hristo Nikolov, Ed F. Deprettere. 30-37 [doi]
- Modular high-throughput and low-latency sorting units for FPGAs in the Large Hadron ColliderAmin Farmahini Farahani, Anthony E. Gregerson, Michael J. Schulte, Katherine Compton. 38-45 [doi]
- Memory-efficient volume ray tracing on GPU for radiotherapyBo Zhou, Xiaobo Sharon Hu, Danny Z. Chen. 46-51 [doi]
- System integration of Elliptic Curve Cryptography on an OMAP platformSergey Morozov, Christian Tergino, Patrick Schaumont. 52-57 [doi]
- ISIS: An accelerator for Sphinx speech recognitionAnthony Chun, Jenny X. Chang, Zhen Fang, Ravishankar Iyer, Michael Deisher. 58-61 [doi]
- Dynamically reconfigurable architecture for a driver assistant systemNaim Harb, Smaïl Niar, Mazen A. R. Saghir, Yassin Elhillali, Rabie Ben Atitallah. 62-65 [doi]
- FPGA based parallel architecture implementation of Stacked Error Diffusion algorithmRishvanth Kora Venugopal, J. Robert Heath, Daniel L. Lau. 66-69 [doi]
- 3D recursive Gaussian IIR on GPU and FPGAs - A case for accelerating bandwidth-bounded applicationsJason Cong, Muhuan Huang, Yi Zou. 70-73 [doi]
- A fast CUDA implementation of agrep algorithm for approximate nucleotide sequence matchingHongjian Li, Bing Ni, Man Hon Wong, Kwong-Sak Leung. 74-77 [doi]
- Frameworks for GPU Accelerators: A comprehensive evaluation using 2D/3D image registrationRichard Membarth, Frank Hannig, Jürgen Teich, Mario Körner, Wieland Eckert. 78-81 [doi]
- A massively parallel implementation of QC-LDPC decoder on GPUGuohui Wang, Michael Wu, Yang Sun, Joseph R. Cavallaro. 82-85 [doi]
- ARTE: An Application-specific Run-Time management framework for multi-core systemsGiovanni Mariani, Gianluca Palermo, Cristina Silvano, Vittorio Zaccaria. 86-93 [doi]
- A hardware acceleration technique for gradient descent and conjugate gradientDavid Kesler, Biplab Deka, Rakesh Kumar. 94-101 [doi]
- A multi-threaded coarse-grained array processor for wireless basebandTom Vander Aa, Martin Palkovic, Matthias Hartmann, Praveen Raghavan, Antoine Dejonghe, Liesbet Van der Perre. 102-107 [doi]
- Hardware/software co-designed accelerator for vector graphics applicationsShuo-Hung Chen, Hsiao-Mei Lin, Hsin-Wen Wei, Yi-Cheng Chen, Chih-Tsun Huang, Yeh-Ching Chung. 108-114 [doi]
- Scalable object detection accelerators on FPGAs using custom design space explorationChen Huang, Frank Vahid. 115-121 [doi]
- A parallel accelerator for semantic searchAbhinandan Majumdar, Srihari Cadambi, Srimat T. Chakradhar, Hans Peter Graf. 122-128 [doi]
- A novel parallel Tier-1 coder for JPEG2000 using GPUsRoto Le, R. Iris Bahar, Joseph L. Mundy. 129-136 [doi]