Abstract is missing.
- RTL power estimation and optimizationEnrico Macii. 1 [doi]
- Statistical analysis and design: from picoseconds to probabilitiesChandu Visweswariah. 2 [doi]
- Architecture and CAD for FPGAsMike Hutton. 3 [doi]
- Test and design-for-test of mixed-signal integrated circuitsJosé Luis Huertas. 4 [doi]
- Will the ASIC survive?Raul Camposano. 5 [doi]
- Avionic systems overviewArmando Carbonari. 6 [doi]
- Leakage power optimization in standard-cell designsEnrico Macii. 7 [doi]
- Advances and trends in FPGA designMike Hutton. 8 [doi]
- Verification and test challenges in SoC designsCésar Augusto Dueñas M.. 9 [doi]
- PaDReH: a framework for the design and implementation of dynamically and partially reconfigurable systemsEwerson Carvalho, Ney Calazans, Eduardo Wenzel Brião, Fernando Moraes. 10-15 [doi]
- A partial reconfigurable architecture for controllers based on Petri netsPaulo Sérgio B. do Nascimento, Paulo Romero Martins Maciel, Manoel Eusebio de Lima, Remy Eskinazi Sant Anna, Abel Guilhermino S. Filho. 16-21 [doi]
- Task scheduling for heterogeneous reconfigurable computersAli Ahmadinia, Christophe Bobda, Dirk Koch, Mateusz Majer, Jürgen Teich. 22-27 [doi]
- Real-time LUT-based network topologies for dynamic and partial FPGA self-reconfigurationMichael Hübner, Tobias Becker, Jürgen Becker. 28-32 [doi]
- Characterization of MOS transistor current mismatchHamilton Klimach, Alfredo Arnaud, Márcio C. Schneider, Carlos Galup-Montoro. 33-38 [doi]
- A 0.8 mum CMOS switched-capacitor video filterAntonio Petraglia, Jorge M. Cañive, Mariane R. Petraglia. 39-43 [doi]
- A 1.8V supply multi-frequency digitally trimmable on-chip IC oscillator with low-voltage detection capabilityAndre Vilas Boas, J. B. D. Soldera, Alfredo Olmos. 44-48 [doi]
- Modeling and designing high performance analog reconfigurable circuitsEric E. Fabris, Luigi Carro, Sergio Bampi. 49-54 [doi]
- Exception handling in microprocessors using assertion librariesFernando Cortez Sica, Claudionor José Nunes Coelho Jr., José Augusto Miranda Nacif, Harry Foster, Antônio Otávio Fernandes. 55-59 [doi]
- TheoSim: combining symbolic simulation and theorem proving for hardware verificationGhiath Al Sammane, Julien Schmaltz, Diana Toma, Pierre Ostier, Dominique Borrione. 60-65 [doi]
- An automatic testbench generation tool for a SystemC functional verification methodologyKarina R. G. da Silva, Elmar U. K. Melcher, Guido Araujo, Valdiney Alves Pimenta. 66-70 [doi]
- A multi-level approach to the dependability analysis of networked systems based on the CAN protocolFulvio Corno, Julio Pérez Acle, Matteo Sonza Reorda, Massimo Violante. 71-75 [doi]
- Design sequence for a LC-tank voltage controlled oscillator in CMOS for RFJosé Vieira do Vale Neto. 76-81 [doi]
- Design of RF CMOS low noise amplifiers using a current based MOSFET modelVirgínia Helena Varotto Baroncini, Oscar da Costa Gouveia-Filho. 82-87 [doi]
- Dual-mode RF receiver front-end using a 0.25-µm 60-GHz f::T::SiGe: C BiCMOS7RF technologyC. P. Moreira, Eric Kerherve, P. Jarry, A. A. Shirakawa, Didier Belot. 88-93 [doi]
- A 4 GHz dual modulus divider-by 32/33 prescaler in 0.35m CMOS technologyFernando P. H. de Miranda, João Navarro Jr., Wilhelmus A. M. Van Noije. 94-99 [doi]
- ATPG for fault diagnosis on analog electrical networks using evolutionary techniquesCarlos Eduardo Savioli, Claudio C. Czendrodi, José Vicente Calvano, Antonio Carneiro de Mesquita Filho. 100-104 [doi]
- Improving mixed-signal SOC testing: a power-aware reuse-based approach with analog BISTAntonio Andrade Jr., Érika F. Cota, Marcelo Lubaszewski. 105-110 [doi]
- Reducing test time with processor reuse in network-on-chip based systemsAlexandre M. Amory, Érika F. Cota, Marcelo Lubaszewski, Fernando Gehm Moraes. 111-116 [doi]
- Accurate capture of timing parameters in inductively-coupled on-chip interconnectsTudor Murgan, Clemens Schlachta, Mihail Petrov, Leandro Soares Indrusiak, Alberto García Ortiz, Manfred Glesner, Ricardo A. L. Reis. 117-122 [doi]
- Issues in parallelizing multigrid-based substrate model extraction and analysisJoão M. S. Silva, L. Miguel Silveira. 123-128 [doi]
- An approach to computer simulation of bonding and package crosstalk in mixed-signal CMOS ICsGabriella Trucco, Giorgio Boselli, Valentino Liberali. 129-134 [doi]
- Distributed arithmetic FPGA design with online scalable size and performanceKlaus Danne. 135-140 [doi]
- Adaptive DMA-based I/O interfaces for data stream handling in multi-grained reconfigurable hardware architecturesAlexander Thomas, Thomas Zander, Jürgen Becker. 141-146 [doi]
- An ultra-low-power self-biased current referenceEdgar Mauricio Camacho-Galeano, Carlos Galup-Montoro, Márcio C. Schneider. 147-150 [doi]
- A fully integrated physical activity sensing circuit for implantable pacemakersAlfredo Arnaud, Carlos Galup-Montoro. 151-156 [doi]
- A VLIW low power Java processor for embedded applicationsAntonio Carlos Schneider Beck, Luigi Carro. 157-162 [doi]
- A formal software synthesis approach for embedded hard real-time systemsRaimundo S. Barreto, Marília Neves, Meuse N. Oliveira Jr., Paulo Romero Martins Maciel, Eduardo Tavares, Ricardo Massa Ferreira Lima. 163-168 [doi]
- Power and performance tuning in the synthesis of real-time scheduling algorithms for embedded applicationsLeandro Buss Becker, Marco A. Wehrmeister, Carlos Eduardo Pereira. 169-174 [doi]
- Accurate software performance estimation using domain classification and neural networksMárcio Oyamada, Felipe Zschornack, Flávio Rech Wagner. 175-180 [doi]
- Enhanced 32-bit carry lookahead adder using multiple output enable-disable CMOS differential logicMário C. B. Osorio, Carlos A. Sampaio, André Inácio Reis, Renato P. Ribas. 181-185 [doi]
- A programmable cellular neural network circuitMichel Leong, Pedro Vasconcelos, Jorge R. Fernandes, Leonel Sousa. 186-191 [doi]
- A multi-standard channel-decoder for base-station applicationsTimo Vogt, Norbert Wehn, Philippe Alves. 192-197 [doi]
- FPGA implementation of parallel turbo-decodersMichael J. Thul, Norbert Wehn. 198-203 [doi]
- ParIS: a parameterizable interconnect switch for networks-on-chipCesar Albenes Zeferino, Frederico G. M. E. Santo, Altamiro Amadeu Susin. 204-209 [doi]
- A switch architecture and signal synchronization for GALS system-on-chipsPeter Zipf, Heiko Hinkelmann, Adeel Ashraf, Manfred Glesner. 210-215 [doi]
- When reconfigurable architecture meets network-on-chipRodrigo Soares, Ivan Saraiva Silva, Arnaldo Azevedo. 216-221 [doi]
- On the dynamic behavior of a novel digital-only sigma--delta A/D converterMarcel Jacomet, Josef Goette, Venanz Zbinden, Christian Narvaez. 222-227 [doi]
- Digital background and blind calibration for clock skew error in time-interleaved analog-to-digital convertersDavid Camarero, Jean-François Naviner, Patrick Loumeau. 228-232 [doi]
- A low power 13-Gb/s 2^7-1 pseudo random bit sequence generator IC in 120 nm bulk CMOSHans-Dieter Wohlmuth, Daniel Kehrer. 233-236 [doi]
- An improved synthesis method for low power hardwired FIR filtersVagner S. Rosa, Eduardo A. C. da Costa, José C. Monteiro, Sergio Bampi. 237-241 [doi]
- A SystemC based case study of a sensor application using the BeCom modeling methodology for virtual prototypingChristian Meise, Christoph Grimm. 242-247 [doi]
- Modeling and prototyping dynamically reconfigurable systems for efficient computation of dynamic programming methods by rewriting-logicMauricio Ayala-Rincón, Ricardo P. Jacobi, Luis G. A. Carvalho, Carlos H. Llanos, Reiner W. Hartenstein. 248-253 [doi]
- Advanced technology mapping for standard-cell generatorsVinícius Correia, André Reis. 254-259 [doi]
- Non-Manhattan maze routingMircea R. Stan, Fatih Hamzaoglu, David Garrett. 260-265 [doi]
- Body-bias compensation technique for SubThreshold CMOS static logic gatesLuiz Alberto P. Melek, Márcio C. Schneider, Carlos Galup-Montoro. 267-272 [doi]
- Low-power dual V::th:: pseudo dual V::dd:: domino circuitsYuvraj Singh Dhillon, Abdulkadir Utku Diril, Abhijit Chatterjee, Adit D. Singh. 273-277 [doi]
- Low power gate-level design with mixed-V::th:: (MVT) techniquesFrank Sill, Frank Grassert, Dirk Timmermann. 278-282 [doi]