Table of Contents

• Sparse severe error removal in OFDM demodulators for erasure channelsRenfei Liu, Keshab K. Parhi. 1-6 [doi]
• A novel circulant approximation method for frequency domain LMMSE equalizationClemens Buchacher, Joachim Wehinger, Mario Huemer. 7-12 [doi]
• Multi-level modulation soft-decision demapper for DVB-S2Jang Woong Park, Myung Hoon Sunwoo, Pansoo Kim, Dae-Ig Chang. 13-17 [doi]
• Design of rotated QAM mapper/demapper for the DVB-T2 standardMeng Li, Charbel Abdel Nour, Christophe Jégo, Catherine Douillard. 18-23 [doi]
• Register file exploration for a multi-standard wireless forward error correction ASIPPraveen Raghavan, Francky Catthoor. 24-29 [doi]
• Implementation of the W-CDMA cell search on a MPSOC designed for software defined radiosFabio Garzia, Roberto Airoldi, Tapani Ahonen, Jari Nurmi, Dragomir Milojevic. 30-35 [doi]
• Two-parallel concatenated BCH super-FEC architecture for 100-GB/S optical communicationsSangho Yoon, Hanho Lee, Kihoon Lee, Chang-Seok Choi, Jongyoon Shin, Jongho Kim, Je Soo Ko. 36-39 [doi]
• Low-power implementation of a high-throughput LDPC decoder for IEEE 802.11N standardJunho Cho, Naresh R. Shanbhag, Wonyong Sung. 40-45 [doi]
• Low-complexity frame-size down-scaling integrated with IDCTMeng-Lin Hsia, Chih-Feng Tseng, Meng-Hsuan Chan, Oscal T.-C. Chen. 46-50 [doi]
• Is the differential frequency-based attack effective against random delay insertion?Yingxi Lu, Keanhong Boey, Maire P. O Neill, John V. McCanny, Akashi Satoh. 51-56 [doi]
• Approximating sine functions using variable-precision Taylor polynomialsClaudio Brunelli, Heikki Berg, David Guevorkian. 57-62 [doi]
• Reducing processor energy consumption by compiler optimizationVladimír Guzma, Teemu Pitkänen, Pertti Kellomäki, Jarmo Takala. 63-68 [doi]
• Hardware reduction methodology for 2-dimensional kurtotic fastica based on algorithmic analysis and architectural symmetryAmit Acharyya, Koushik Maharatna, Bashir M. Al-Hashimi. 69-74 [doi]
• Parallel object detection on multicore platformsShin-Kai Chen, Tay-Jyi Lin, Chih-Wei Liu. 75-80 [doi]
• Reconfigurable video decoder with transform accelerationLassi Nurmi, Perttu Salmela, Pertti Kellomäki, Pekka Jääskeläinen, Jarmo Takala. 81-86 [doi]
• SIMD processor based implementation of recursive filtering equationsJae-Woo Ahn, Hoseok Chang, Junho Cho, Wonyong Sung. 87-92 [doi]
• An adaptive fast multiple reference frame selection algorithm for H.264/AVC using reference region dataKangjun Lee, Gwanggil Jeon, Rafael Falcón, Changwoo Ha, Jechang Jeong. 93-96 [doi]
• An early block type decision method for intra prediction in H.264/AVCJungho Do, Sangkwon Na, Chong-Min Kyung. 97-101 [doi]
• Design of an interlayer deblocking filter architecture for H.264/SVC based on a novel sample-level filtering orderGuilherme Corrêa, Thaísa Leal da Silva, Luís A. Cruz, Luciano Volcan Agostini. 102-108 [doi]
• Fast pipeline schedule for an H.264 intra frame encoder with early terminationYoung-Joon Jo, Jin-Su Jung, Hyuk-Jae Lee. 109-114 [doi]
• Architectural support for the orchestration of fine-grained multiprocessing for portable streaming applicationsJani Boutellier, Alessandro Cevrero, Philip Brisk, Paolo Ienne. 115-120 [doi]
• FPGA architecture for 2D Discrete Fourier Transform based on 2D decomposition for large-sized dataJungsub Kim, Chi-Li Yu, Lanping Deng, Srinidhi Kestur, Vijaykrishnan Narayanan, Chaitali Chakrabarti. 121-126 [doi]
• System level DSP synthesis using voltage overscaling, unequal error protection & adaptive quality tuningGeorgios Karakonstantis, Debabrata Mohapatra, Kaushik Roy. 133-138 [doi]
• Loop scheduling with memory access reduction under register constraints for DSP applicationsMeng Wang, Duo Liu, Yi Wang, Zili Shao. 139-144 [doi]
• Interface-based hierarchy for synchronous data-flow graphsJonathan Piat, Shuvra S. Bhattacharyya, Mickaël Raulet. 145-150 [doi]
• Power-aware evaluation flowfor digital decimation filter architectures for high-speed ADCSDavid Novo, Robert Fasthuber, Praveen Raghavan, André Bourdoux, Min Li, Liesbet Van der Perre, Francky Catthoor. 151-156 [doi]
• Locally adaptive speckle noise reduction using maximum a posteriori estimation based on Maxwell distributionSung Gug Kim, Yoo Shin Kim, Il Kyu Eom. 157-160 [doi]
• HybridKernel: Preemptive kernel with event-driven extension for resource constrained wireless sensor networksTeemu Laukkarinen, Ville Kaseva, Jukka Suhonen, Timo D. Hämäläinen, Marko Hännikäinen. 161-166 [doi]
• Morphable DPU: Smart and efficient data path for signal processing applicationsMuhammad Ali Shami, Ahmed Hemani. 167-172 [doi]
• Configurable high-performance video platform using multiple RISC clusters connected with separated data and control networksDaewoong Kim, Kilhyung Cha, Soonwoo Choi, Soo-Ik Chae. 173-178 [doi]
• High-speed area-efficient versatile Reed-Solomon decoder design for multi-mode applicationsBo Yuan, Li Li, Zhongfeng Wang. 179-184 [doi]
• Low-power pre-decoding based viterbi decoder for tail-biting convolutional codesRami A. Abdallah, Seok-Jun Lee, Manish Goel, Naresh R. Shanbhag. 185-190 [doi]
• CAC CODEC designs based on numeral systemsXuebin Wu, Zhiyuan Yan. 191-196 [doi]
• Robust tree construction and maintenance for global time synchronization protocols in Wireless Sensor NetworksVille Kaseva, Timo D. Hämäläinen, Marko Hännikäinen. 197-201 [doi]
• A new FPGA-based postprocessor architecture for channel mismatch correction of time interleaved ADCSAsgar Abbaszadeh, Khosrov Dabbagh-Sadeghipour. 202-207 [doi]
• Rectangular constellation-based blind equalization with recursive least-squares algorithmJuuso Alhava, Markku Renfors. 208-213 [doi]
• An ultra-low-power VAD hardware implementation for intelligent ubiquitous sensor networksHiroki Noguchi, Tomoya Takagi, Masahiko Yoshimoto, Hiroshi Kawaguchi. 214-219 [doi]
• Conflict resolution for pipelined layered LDPC decodersCedric Marchand, Jean-Baptiste Dore, Laura Conde-Canencia, Emmanuel Boutillon. 220-225 [doi]
• A Channel-Adaptive Early Termination strategy for LDPC decodersYu-Hsin Chen, Yi-Ju Chen, Xin-Yu Shih, An-Yeu Wu. 226-231 [doi]
• Bidirectional interleavers for LDPC decoders using transmission gatesKevin Cushon, Warren J. Gross, Shie Mannor. 232-237 [doi]
• An improved min-sum based column-layered decoding algorithm for LDPC codesJun Lin, Jin Sha, Zhongfeng Wang, Li Li. 238-242 [doi]
• A novel trace-pipelined binary arithmetic coder architecture for JPEG2000Minsoo Rhu, In-Cheol Park. 243-248 [doi]
• Software designs of image processing tasks with incremental refinement of computationDavide Anastasia, Yiannis Andreopoulos. 249-254 [doi]
• Memory access characteristics of H.264 video encoder on embedded processorEero Aho, Kimmo Kuusilinna, Jari Nikara. 255-260 [doi]
• Optimal dual frequency combination for Galileo mass market receiver basebandHeikki Hurskainen, Elena Simona Lohan, Jari Nurmi, Stephan Sand, Christian Mensing, Marco Detratti. 261-266 [doi]
• Enhancing GNSS signal acquisition through the Gradient methodAntonio Cavaleri, Letizia Lo Presti, Marco Pini. 267-272 [doi]
• A RAIM approach to GNSS outlier and cycle slip detection using L1 carrier phase time-differencesMartti Kirkko-Jaakkola, Johannes Traugott, Dennis Odijk, Jussi Collin, Gottfried Sachs, Florian Holzapfel. 273-278 [doi]
• OpenCL embedded profile prototype in mobile deviceJyrki Leskela, Jarmo Nikula, Mika Salmela. 279-284 [doi]
• Massively parallel implementation of cyclic LDPC codes on a general purpose graphics processing unitHyunwoo Ji, Junho Cho, Wonyong Sung. 285-290 [doi]
• Development and evaluation of scalable video motion estimators on GPUSvetislav Momcilovic, Leonel Sousa. 291-296 [doi]
• Real-time Motion Estimation for 1080p videos on graphics processing units with shared memory optimizationShang-Te Yang, Tsung-Kai Lin, Shao-Yi Chien. 297-302 [doi]
• A GPU implementation of a real-time MIMO detectorMichael Wu, Siddharth Gupta, Yang Sun, Joseph R. Cavallaro. 303-308 [doi]
• Processing of synthetic Aperture Radar data with GPGPUCarmine Clemente, Maurizio di Bisceglie, Michele Di Santo, Nadia Ranaldo, Marcello Spinelli. 309-314 [doi]