Abstract is missing.
- Understanding metrics in logic synthesis for routability enhancementVictor N. Kravets, Prabhakar Kudva. 3-5 [doi]
- Error-correction and crosstalk avoidance in DSM bussesKetan N. Patel, Igor L. Markov. 9-14 [doi]
- Switching activity analysis and pre-layout activity prediction for FPGAsJason Helge Anderson, Farid N. Najm. 15-21 [doi]
- Sequential delay budgeting with interconnect predictionChao-Yang Yeh, Malgorzata Marek-Sadowska. 23-30 [doi]
- Placement rent exponent calculation methods, temporal behaviour and FPGA architecture evaluationJoachim Pistorius, Mike Hutton. 31-38 [doi]
- Validation of wire length distribution models on commercial designsMartijn T. Bennebroek. 41 [doi]
- Fast estimation of the partitioning rent characteristic using a recursive partitioning modelJoni Dambre, Dirk Stroobandt, Jan Van Campenhout. 45-52 [doi]
- Perimeter-degree: a priori metric for directly measuring and homogenizing interconnection complexity in multilevel placementNavaratnasothie Selvakkumaran, Phiroze N. Parakh, George Karypis. 53-59 [doi]
- Accurate pseudo-constructive wirelength and congestion estimationAndrew B. Kahng, Xu Xu. 61-68 [doi]
- Estimation of wirelength reduction for lambda-geometry vs. manhattan placement and routingHongyu Chen, Chung-Kuan Cheng, Andrew B. Kahng, Ion I. Mandoiu, Qinke Wang. 71-76 [doi]
- A-priori wirelength and interconnect estimation based on circuit characteristicsShankar Balachandran, Dinesh Bhatia. 77-84 [doi]
- Prediction of interconnect pattern density distribution: derivation, validation, and applicationsPayman Zarkesh-Ha, Ken Doniger, William Loh, Peter Wright. 85-91 [doi]
- Early electrical wire projections and implicationsEli Chiprout. 95 [doi]
- Wire length prediction in constraint driven placementQinghua Liu, Bo Hu, Malgorzata Marek-Sadowska. 99-105 [doi]
- Maximum multiplicity distributions (MMD)Pranav Anbalagan, Jeffrey A. Davis. 107-113 [doi]
- System level interconnect design for network-on-chip using interconnect IPsJian Liu, Meigen Shen, Li-Rong Zheng, Hannu Tenhunen. 117-124 [doi]
- Global interconnect trade-off for technology over memory modules to application level: case studyAntonis Papanikolaou, Miguel Miranda, Francky Catthoor, Henk Corporaal, Hugo De Man, David De Roest, Michele Stucchi, Karen Maex. 125-132 [doi]
- A hierarchical three-way interconnect architecture for hexagonal processorsFeng Zhou, Esther Y. Cheng, Bo Yao, Chung-Kuan Cheng, Ronald L. Graham. 133-139 [doi]