Abstract is missing.
- Mobile system considerations for SDRAM interface trendsAndrew B. Kahng, Vaishnav Srinivas. 1-8 [doi]
- System interconnect design exploration for embedded MPSoCsChen-Ling Chou, Radu Marculescu, Ümit Y. Ogras, Satrajit Chatterjee, Michael Kishinevsky, Dmitrii Loukianov. 1-8 [doi]
- Reducing energy and increasing performance with traffic optimization in many-core systemsGeorge B. P. Bezerra, Stephanie Forrest, Payman Zarkesh-Ha. 1-7 [doi]
- Performance and power analysis of through silicon via based 3D IC integrationHung Viet Nguyen, Myunghwan Ryu, Youngmin Kim. 1 [doi]
- Simulation based study of on-chip antennas for a reconfigurable hybrid 2D wireless network-on-chipAnkit More, Baris Taskin. 1 [doi]
- Distributed power network co-design with on-chip power supplies and decoupling capacitorsSelçuk Köse, Eby G. Friedman. 1-5 [doi]
- Toward PDN resource estimation: A law of general power densityKwangok Jeong, Andrew B. Kahng. 1-6 [doi]
- Wirelength and congestion estimation for routability-driven placementYang-Yang Li, Logan M. Rakai, Laleh Behjat, Bill Swartz. 1 [doi]
- A SAT-based routing algorithm for cross-referencing biochipsPing-Hung Yuh, Cliff Chiung-Yu Lin, Tsung-Wei Huang, Tsung-Yi Ho, Chia-Lin Yang, Yao-Wen Chang. 1-7 [doi]
- Stability and scalability in global routingSung Kyu Han, Kwangok Jeong, Andrew B. Kahng, Jingwei Lu. 1-6 [doi]
- Impact of nano-scale through-silicon vias on the quality of today and future 3D IC designsDaehyun Kim, Suyoun Kim, Sung Kyu Lim. 1-8 [doi]
- Architecture and performance evaluation of 3D CMOS-NEM FPGAChen Dong, Chen Chen, Subhasish Mitra, Deming Chen. 1-8 [doi]
- Interface optimization for improved routability in chip-package-board co-designTilo Meister, Jens Lienig, Gisbert Thomke. 1-8 [doi]