Abstract is missing.
- Multi-Die Heterogeneous FPGAs: How Balanced Should Netlist Partitioning be?Raveena Raikar, Dirk Stroobandt. [doi]
- An Automated Design Methodology for Computational SRAM Dedicated to Highly Data-Centric Applications: Invited PaperA. Philippe, Lorenzo Ciampolini, A. Philippe, M. Gerbaud, M. Ramirez-Corrales, Valentin Egloff, Bastien Giraud, Jean-Philippe Noël. [doi]
- Machine-Learning Based Delay Prediction for FPGA Technology MappingHailiang Hu, Jiang Hu, Fan Zhang, Bing Tian, Ismail Bustany. [doi]
- Opportunities of Chip Power Integrity and Performance Improvement through Wafer Backside (BS) Connection: Invited PaperRongmei Chen, Giuliano Sisto, Odysseas Zografos, Dragomir Milojevic, Pieter Weckx, Geert Van der Plas, Eric Beyne. [doi]
- A Machine Learning Approach for Accelerating SimPL-Based Global Placement for FPGA'sTianyi Yu, Nima Karimpour Darav, Ismail Bustany, Mehrdad Eslami Dehkordi. [doi]
- Limiting Interconnect Heating in Power-Driven Physical SynthesisXiuyan Zhang, Shantanu Dutt. [doi]
- Neural Network Model for Detour Net PredictionJaehoon Ahn, Taewhan Kim. [doi]