Table of Contents

• Integration of CMOS Photodiode and Capacitive Charge Pump Circuits for On Chip Photovoltaic Energy HarvestingMacit Uluda, Ali Emir Oktem, Günhan Dündar, Arda D. Yalcinkaya. 1-4 [doi]
• Design of Ultra Wideband Power Divider/Combiner and Comparison on Results of Measurement and Simulation based on EM Solver MethodsEngin Çagdas, Hakan Çetinkaya, Oguzhan Kizilbey, Metin Yazgi. 1-4 [doi]
• Thermal Modeling of Silicon Photonic WaveguidesMatthias Thiele, Jens Lienig, Menglong He, Kambiz Jamshidi. 1-4 [doi]
• An LLM-assisted Analog IC Design Tool with Automatic Topology Selection and Circuit SizingAnh Nguyen, Chien-Nan Jimmy Liu. 1-4 [doi]
• A Microfluidic Refreshable Braille Display SystemÖmer Gökalp Akcan, Özlem Koçoglu, Ahmet Can Erten, Onur Ferhanoglu. 1-4 [doi]
• Temperature Sensors in FPGA Based On Digital Nonlinear Oscillators for Improved SensitivityRaúl Aparicio-Téllez, Miguel Garcia-Bosque, Guillermo Díez-Señorans, Santiago Celma. 1-4 [doi]
• SPFD-Based Delay ResynthesisAndrea Costamagna, Chang Meng, Giovanni De Micheli. 1-4 [doi]
• Towards a Reliable PUF Using Organic Thin-Film TransistorsF. de Los Santos-Prieto, Deborah Eric, Marc Porti, Rafael Castro-López, Elisenda Roca, Francisco V. Fernández 0001, Montserrat Nafría. 1-4 [doi]
• Investigation of Reconfigurable CORDIC Modes and EfficiencyHisham M. Elrefai, Wafaa S. Sayed, Ahmed G. Radwan, Lobna A. Said. 1-4 [doi]
• On the Usage of Genetic Algorithms, Reinforcement Learning and Bayesian Optimisation for RF IC Design AutomationMargarida Lourenço, Bingbing Zhao, Junde Li, Marcelino B. Santos, Pui-In Mak, Rui Paulo Martins, Wei-Han Yu, Fábio Passos. 1-4 [doi]
• High-speed, low-power comparators utilizing a self-cascode configuration and a dynamically biased preamplifier techniqueMohammad Bayazi, Renato Negra. 1-4 [doi]
• Low Voltage Bandgap Reference using Intelligent Layout Generators in 22 nm FDSOI CMOSAdilet Dossanov, Zhaoqun Guo, Uwe Eichler, Benjamin Prautsch, Vadim Issakov. 1-4 [doi]
• An Energy-Efficient Analog Integrated Neural Network for Cirrhosis Patient Survival PredictionKonstantinos Cheliotis, Vassilis Alimisis, Vasileios Moustakas, Zisis Foufas, Anna Mylona, Paul P. Sotiriadis. 1-4 [doi]
• A Cost-Efficient Implementation of an SSVEP-Based Brain-Controlled Robotic Arm SystemHongliang Chen, Weiwei Shi. 1-4 [doi]
• An Efficient Framework for Fully Automated Post-layout Simulation-based OptimizationVeeti Lahtinen, Altti Heikkinen, Santeri Porrasmaa, Aleksi Tamminen, Marko Kosunen. 1-4 [doi]
• EMSpice 2.1: A Coupled EM and IR Drop Analysis Tool with Joule Heating and Thermal Mapb Integration for VLSI ReliabilitySubed Lamichhane, Haotian Lu 0002, Sheldon X.-D. Tan. 1-4 [doi]
• NNHC - a Neural Network to Hardware CompilerSascha Schmalhofer, Yasmine Abu Haeyeh, Lars Hedrich. 1-4 [doi]
• Behavioral Modeling of Analog Neural Networks Inference CircuitsYasmine Abu Haeyeh, Sascha Schmalhofer, Lars Hedrich. 1-4 [doi]
• TERORO - Transient Effect Ring Oscillator and Ring Oscillator Configurable Hybrid PUFAlejandro Casado-Galán, J. Núñez-Martínez, Erica Tena-Sánchez, Francisco Eugenio Potestad-Ordóñez, Antonio J. Acosta 0001. 1-4 [doi]
• RadiSPICE-L: A Layout-Centric Tool for Radiation-Aware Analog Circuit DesignÖmer Yusuf Muhikanci, Kemal Ozanoglu, Engin Afacan, Günhan Dündar. 1-4 [doi]
• A 1 Gb/s PAM-8 Variable-Gain Transimpedance Amplifier (VG-TIA) in 180 nm CMOS TechnologyFikriye Elif Karakuzu, Eray Kütük, Arda Yildiz, Irem Cömertoglu, Ali Dogus Güngördü, Mustafa Berke Yelten. 1-4 [doi]
• Application of the Expert Design Plan Methodology on an Ultra-Low-Power Sensor FrontendLorenz Renner, Ralf Sommer, Yannick Uhlmann. 1-4 [doi]
• Implementation of a Linear LN-TIA with PMOS Resistors in a T-network ConfigurationHakan Çetinkaya, Yasin Talay. 1-4 [doi]
• Multimodal IoT Device Authentication using Behavioral and Physical Unclonable Functions and Kyber Public Key EncryptionRoberto Román, Rosario Arjona, Iluminada Baturone. 1-5 [doi]
• Verification of RISC-V R-type Instructions Using A Custom Cocotb Based ApproachSennur Güney, Ihsan Çiçek. 1-4 [doi]
• Technology-Independent Local Mismatch Estimation Using Precomputed Lookup TablesKareem H. Khattab, Muh-Dey Wei, Renato Negra. 1-4 [doi]
• Design of a Low-Noise Amplifier for Qubit ReadoutGabriel López-Pinar, Uxua Esteban-Eraso, Santiago Celma, Carlos Sánchez-Azqueta. 1-4 [doi]
• SystemVerilog-Based Modeling and Verification of 40-Gb/s/Lane PAM-3 Transmitter for USB4.0 Gen4Yong-Gyu Yu, Ju-Hyeong Yun, Chae-Hyeon Lim, Joo-Hyung Chae. 1-4 [doi]
• Simulink-Based HDL Design: A Case Study on Harmonic Control Arrays Algorithm RealizationAkif Altintas, Muhammed Yusufoglu, Ugur Cini, Murat Dogruel. 1-4 [doi]
• Power Amplifier Modeling along with Hyperparameter Optimization of LSTM-based DNN through Multi-Verse OptimizerLida Kouhalvandi, Sercan Aygun, Serdar Özoguz, Ladislau Matekovits, M. Hassan Najafi, Saeid Karamzadeh. 1-4 [doi]
• FPGA-based Neural Network for Arabic and English Handwritten Digit RecognitionAbdulrahman Elsadiq, Hisham M. Elrefai, Lobna A. Said. 1-4 [doi]
• Dark Current Analysis in Silicon PIN Photodetectors: TCAD, Lifetime and Statistical Process ControlYigithan Mehmet Kose, Utku Guney, Elcin Mert, Dilek Alimli. 1-4 [doi]
• Hybrid AI-Optimization Method for Latent Defect Detection Through Test Transistor Insertion in Analog CircuitsSankhya Bhattacharya, Georges G. E. Gielen. 1-4 [doi]
• Ternary PUF-based Secure Mutual Authentication Using RNNs for Sequence Learning in Response ClassificationJoseph He Chang, Shekoufeh Neisarian, Nico Mexis, Nikolaos Athanasios Anagnostopoulos, Tolga Arul, Elif Bilge Kavun. 1-4 [doi]
• Optically Powered Sub-1 dB Noise Figure CMOS LNA for Magnetic Resonance ImagingMert Sentürk, Günhan Dündar, Arda Deniz Yalcinkaya. 1-4 [doi]
• A Low-Power Charge-Pump PLL for Sub-6 GHz 5G and IoT Wireless Communication SystemsMert Korkut, Tugba Haykir Ergin, Hüseyin Arda Ülkü. 1-4 [doi]
• CAD Modeling of a Wafer-Level Packaging GaN Transistors for Electrothermal Simulation Using the Finite Element MethodMohamed Belguith, Sonia Eloued, Moncef Kadi, Jaleleddine Ben Hadj Slama, Mahmoud Hamouda. 1-4 [doi]
• Hardware-Software Co-Design for Resource Efficient Gesture Classification System for FPGAsRashed Al Amin, Roman Obermaisser. 1-4 [doi]
• Sorting Errors Effects on Optimal Combination Algorithms for Digital-to-Analog ConvertersFrancesco Gagliardi 0002, Massimo Piotto, Paolo Bruschi, Michele Dei. 1-4 [doi]
• ATOMIC: Automatic Tool for Memristive IMPLY based Circuit-level Simulation and ValidationFabian Seiler, Peter M. Hinkel, Axel Jantsch, Nima Taherinejad. 1-4 [doi]
• A Scalable Authentication Scheme for Detecting Unauthorized Dice in A Multi-Die ICZheng-Hao Wang, Shi-Yu Huang, Chi-Kang Chen. 1-4 [doi]
• Dynamic Analysis of OOK Modulators Using Eye Diagrams to Assess Data Rate and Output MatchingAhmet Yelboga, Korkut Kaan Tokgoz. 1-4 [doi]
• A Compact Flexible High-bandwidth Meander Line Patch Antenna for IoT ApplicationsMehmet Selim Mamati, Seref Keser, M. A. Alsunaidi. 1-4 [doi]
• Technology-independent Layout Generator of Industry-grade Power Devices Validated Down to 22-nm NodesDuarte Marques, Ricardo Martins, Marcelino B. Santos. 1-4 [doi]
• 2DD? An Energy Model for Compute-in-Memory SRAM CellsSimon Wilhelmstätter, Joschua Conrad, Johannes Stark, Devanshi Upadhyaya, Maël Gay, Ilia Polian, Maurits Ortmanns. 1-4 [doi]
• A Novel 10-18 GHz Current-Reuse Distributed Cascode Low-Noise Amplifier (LNA) DesignYavuzhan Yavuz, Mustafa Berke Yelten. 1-4 [doi]
• A Hysteretic-Controlled Digital LDO Regulator for Enhanced Load Transient ResponseKartikay Mani Tripathi, Madhav Pathak, Sanjeev Manhas, Anand Bulusu. 1-4 [doi]
• WDP: A Weighted Delay Prediction Method for Integrated Circuit InterconnectsYoonsoo Park, Songnam Hong 0001, Jaeduk Han. 1-4 [doi]
• Process-Portable Layout Generation of High-Speed Digital Circuit Using Standard Cells in FinFETTaeseung Kang, Taeho Shin, Heejun Kim, Jaeduk Han. 1-4 [doi]
• A Practical PCB-based Framework for Spiking Neural Networks with a Half-Adder ExampleSevde Vuslat Çikikci, Eren Örek, Ayhan Aysoy, Ali Kagan Özgen, Arda Yavuz, Tuba Ayhan. 1-4 [doi]
• FET Modeling with Deep Neural Networks and GAN-Augmented Small Measurement DatasetMilad Bafarassat, Melik Yazici, Korkut Kaan Tokgoz. 1-4 [doi]
• A Comparative Study of Switch-Mode and Constant-Current Methods for High-Efficiency Neural StimulationSergio Massaioli, Georges G. E. Gielen. 1-4 [doi]
• SystemVerilog-Based Modeling and Verification of 25.6-GBaud/Lane PAM-3 ReceiverChae-Hyeon Lim, Ju-Hyeong Yun, Yong-Gyu Yu, Joo-Hyung Chae. 1-4 [doi]
• A Low-Voltage, Low-Power CMOS Temperature Sensor Utilizing a Single PTAT-CTAT Current LoopTugce Karpuz, Kemal Ozanoglu, Sumer Can. 1-4 [doi]
• A Side-Channel Attack-Resilient Single-Slope ADC for Image Sensor ApplicationsCeyda Körpe, Kareem Ahmad, Ece Öztürk, Kanishk Tihaiya, Ryanh Tran, Hyunsoo Yang, Junbin Yang, Günhan Dündar, Vincent John Mooney, Kemal Ozanoglu. 1-4 [doi]
• Modeling and Analysis of MS Accelerators Embedding SRAM and RRAM Compute CellsMichele Caselli, Andrea Boni. 1-4 [doi]
• On the Exploration of Convolutional Variational Autoencoders for Analog Integrated Circuit Post-Placement Performance RegressionCarlos Almeida, Marco Oliveira, Ricardo Martins. 1-4 [doi]
• Multi-Objective Optimization of Analog Circuits Using Reinforcement LearningHakan Taskiran, Enes Saglican, Engin Afacan. 1-4 [doi]
• Response Time Analysis of Thin Film Based Piezoresistive Pressure SensorMehmet Akif Ozkaya, Kaan Demirel, Tugberk Taha Yolcu, Korkut Kaan Tokgoz. 1-4 [doi]
• Circuit-Level Modeling and Simulation of Read Disturbance Phenomena: RowHammer and RowPressEda Deniz Demirel, Engin Afacan, Günhan Dündar. 1-4 [doi]
• Ultra-Low Power and Low-Leakage Subthreshold CMOS Neural Circuit DesignMuhammed Efdal Elkatmis, Okan Zafer Batur, Burcu Erkmen. 1-4 [doi]
• A Comparative Study on the Incorporation of PVT Corner Conditions within Reinforcement Learning-based Analog IC Sizing ApproachesJosé Costa, Filipe Azevedo, Ricardo Martins 0003. 1-4 [doi]
• Fault Injection Attacks Based on Layout-Driven SER AnalysisAlexandra Takou, Pelopidas Tsoumanis, Georgios Ioannis Paliaroutis, Nestor E. Evmorfopoulos, George I. Stamoulis. 1-4 [doi]
• A Large Tuning-Range LC-VCO Design for Mixer-First Type ReceiversEmirhan Dilekoglu, Mustafa Berke Yelten. 1-4 [doi]
• An AI-driven EDA Algorithm-Empowered VCO and LDO Co-Design MethodYijia Hao, Maarten Strackx, Miguel Gandara, Sandy Cochran, Bo Liu 0003. 1-4 [doi]
• A Power-Efficient Analog Integrated Decision Tree Classifier for Machine Predictive Maintenance ClassificationVassilis Alimisis, Konstantinos Cheliotis, Vasileios Moustakas, Anna Mylona, Zisis Foufas, Paul P. Sotiriadis. 1-4 [doi]
• 3D Monte Carlo Simulations of n-type Nanowire-FETs: The Effect of Gate ScalingMurad G. K. Alabdullah, N. Seoane, Antonio J. García-Loureiro, K. Kalna. 1-4 [doi]
• Design Space Exploration and Topology Assessment of Low-Power Sleep Comparators Using Evolutionary AlgorithmsEnes Saglican, Hakan Taskiran, Kemal Ozanoglu, Engin Afacan. 1-4 [doi]
• Combining Machine Learning and Optimization Techniques for the High-Level Design of Σ∆MsGustavo Liñán Cembrano, José M. de la Rosa 0001. 1-4 [doi]
• Simulation Study of the Maximum Power Dissipation-Energy Consumption Dilemma in Memristors Using the Dynamic Memdiode ModelEnrique Miranda 0002, E. Piros, Fernando L. Aguirre, X. Pérez, T. Kim, J. P. Schreyer, Jonas Gehrunger, T. Oster, Klaus Hofmann, Jordi Suñé, Christian Hochberger, L. Alff. 1-4 [doi]
• Compact SER Models via Model Order Reduction of Diffusion-Based Charge CollectionPavlos Stoikos, Olympia Axelou, Pelopidas Tsoumanis, Georgios Ioannis Paliaroutis, George Floros 0002. 1-4 [doi]
• Co-Simulation for Automated Optimization of Integrated Cryogenic Qubit ElectronicsPau Dietz Romero, Caner Toprak, Lammert Duipmans, Stefan van Waasen, Lotte Geck. 1-4 [doi]
• Compact SER Models via Model Order Reduction of Diffusion-Based Charge CollectionPavlos Stoikos, Olympia Axelou, Pelopidas Tsoumanis, Georgios Ioannis Paliaroutis, George Floros 0002. 1-4 [doi]
• Inverse Analog IC Sizing and Exploration through Diffusion Models and Structural KnowledgeFilipe Azevedo 0001, Markus Leibl, Ricardo Martins 0003, Helmut Graeb. 1-4 [doi]
• An Open-Source EM Simulation Flow Based on a High-Level Python APICaglar Ozdag, Engin Afacan, Günhan Dündar. 1-4 [doi]
• Fast and Accurate Multi-Neural Network Ensemble ModelVeli Nakçi, Mustafa Altun. 1-4 [doi]
• Characterization of Inter-Chip Interconnects Using Piecewise Effective CapacitanceNilotpal Sarma, Ashutosh Yadav, Sudeb Dasgupta, Anand Bulusu. 1-4 [doi]
• Designing compact phase shifters with a resistorless quadrature signal generatorUxua Esteban-Eraso, Carlos Sánchez-Azqueta, Francisco Aznar, Concepción Aldea, Santiago Celma. 1-4 [doi]
• Prediction of Single Event Transient Propagation Using Machine Learning ModelsMarko S. Andjelkovic, Junchao Chen 0001, Jelisaveta Aleksic, Vishnu Padmakumar, Milos Marjanovic, Nikolaos Zazatis, Trupti Ranjan Lenka, Danijel Dankovic, Christos P. Sotiriou, Fabian Vargas 0001. 1-4 [doi]
• Trust Based Access Control For Dynamically Reconfigurable Sensor NetworkMehmet Onur Demirtürk, Berna Ors. 1-4 [doi]
• Anisotropic and Tunable Vocal Fold Phantom for Biomechanical ModelingAfarin Sarrafzadeh, Kuter Erdil, Onur Tavli, Onur Ferhanoglu, Ahmet Can Erten. 1-4 [doi]
• A QCM-VNA System for Microfluidic Sensing: Leveraging Higher-Order HarmonicsEren Koltuk, Saibe Demir, Eren Yalçin, Kerim Alaz Demir, Ebrar Kahveci, Okan Zafer Batur, Günhan Dündar, Ceyhun Ekrem Kirimli. 1-4 [doi]
• Efficient Guard Ring-Aware Placement for FinFET Analog Circuits with Diffusion SharingShih-Yu Chen, Tzu-Hsiang Wei, Haoju Chang, Hung-Ming Chen, Chien-Nan Jimmy Liu. 1-4 [doi]
• Enhancing Reinforcement Learning for the Floorplanning of Analog ICs with Beam SearchSandro Junior Della Rovere, Davide Basso, Luca Bortolussi, Mirjana S. Videnovic-Misic, Husni Habal. 1-4 [doi]
• Agile Frequency Synthesis for a sub-100µW Wake-up ReceiverShaheeda F. S. Vajrala, G. S. Javed. 1-4 [doi]
• An Open-Source Environment for Evaluating Reinforcement Learning Algorithms for Analog IC FloorplanningTill Moldenhauer, Yannick Uhlmann, Jürgen Scheible. 1-4 [doi]
• Efficient Parameter Reduction for Statistical Behavioral ModelingJan Rödel, Carna Zivkovic, Neha Chavan, Christoph Grimm 0001. 1-4 [doi]