High-Speed, Low-Power 54-B X 54-B Digital Multiplier Architecture Using Redundant Binary - researchr publication bibtex

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Yun Kim. High-Speed, Low-Power 54-B X 54-B Digital Multiplier Architecture Using Redundant Binary. PhD thesis, University of Illinois Urbana-Champaign, USA, 2001. [doi]

@phdthesis{us-8062,
  title = {High-Speed, Low-Power 54-B X 54-B Digital Multiplier Architecture Using Redundant Binary},
  author = {Yun Kim},
  year = {2001},
  url = {https://hdl.handle.net/2142/80749},
  researchr = {https://researchr.org/publication/us-8062},
  cites = {0},
  citedby = {0},
  school = {University of Illinois Urbana-Champaign, USA},
}

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