Haidar M. Harmanani - researchr alias

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Viewing Publication 1 - 22 from 22

2021

A Strength Pareto Evolutionary Algorithm for Solving the Capacitated Vehicle Routing Problem with Time WindowsWissam Marrouche, Haidar M. Harmanani. ijcci 2021: 96-106 [doi]

2018

A Strength Pareto Evolutionary Algorithm for Optimizing System-On-Chip Test SchedulesWissam Marrouche, Rana Farah, Haidar M. Harmanani. ijcia, 17(2):1850010, 2018. [doi]

2016

A single switcher combined series parallel hybrid envelope tracking amplifier for wideband RF power amplifier applicationsNijad Anabtawi, Rony Ferzli, Haidar M. Harmanani. iscas 2016: 2366-2369 [doi]

An enhanced light-load efficiency step down regulator with fine step frequency scalingNijad Anabtawi, Rony Ferzli, Haidar M. Harmanani. iscas 2016: 2695-2698 [doi]

An all-digital fast tracking switching converter with a programmable order loop controller for envelope tracking RF power amplifiersNijad Anabtawi, Rony Ferzli, Haidar M. Harmanani. iscas 2016: 1690-1693 [doi]

2015

An Ant Colony Optimization Heuristic to Optimize Prediction of Stability of Object-Oriented ComponentsHaidar M. Harmanani, Danielle Azar, Grace Zgheib, David Kozhaya. iri 2015: 225-228 [doi]

A Parallel GPU Implementation of the Timber Wolf Placement AlgorithmAhmad Al Kawam, Haidar M. Harmanani. itng 2015: 792-795 [doi]

2014

Efficient shaped quantizer dithering implementation for sigma delta modulatorsNijad Anabtawi, Rony Ferzli, Haidar M. Harmanani. icecsys 2014: 766-769 [doi]

2011

Heuristic approaches for optimizing the performance of rule-based classifiersDanielle Azar, Haidar M. Harmanani. iri 2011: 25-31 [doi]

A Simulated Annealing Algorithm for the Capacitated Vehicle Routing ProblemHaidar M. Harmanani, Danielle Azar, Nathalie Helal, Walid Keirouz. cata 2011: 96-101

An optimal formulation for test scheduling network-on-chip using multiple clock ratesHassan A. Salamy, Haidar M. Harmanani. ccece 2011: 215-218 [doi]

2010

Predicting stability of classes in an object-oriented systemDanielle Azar, Haidar M. Harmanani, Rita Korkmaz. jcmse, 10(3-6):39-49, 2010. [doi]

Estimating test cost during data path and controller synthesis with low power overheadHaidar M. Harmanani, Maya Kodeih. ccece 2010: 1-5 [doi]

2009

A hybrid heuristic approach to optimize rule-based software quality estimation modelsDanielle Azar, Haidar M. Harmanani, Rita Korkmaz. INFSOF, 51(9):1365-1376, 2009. [doi]

A Hybrid Heuristic Approach To Optimize Rule-Based Software Quality Estimation ModelsDanielle Azar, Haidar M. Harmanani, Rita Korkmaz. sede 2009: 91-98

A parallel genetic algorithm for the open-shop scheduling problem using deterministic and random movesHaidar M. Harmanani, Fouad Drouby, Steve Bou Ghosn. springsim 2009: [doi]

2006

A Simulated Annealing Algorithm for System-on-Chip Test Scheduling with, Power and Precedence ConstraintsHaidar M. Harmanani, Hassan A. Salamy. ijcia, 6(4):511-530, 2006. [doi]

Power-Constrained System-on-a-Chip Test Scheduling Using a Genetic AlgorithmHaidar M. Harmanani, Hassan A. Salamy. jcsc, 15(3):331-349, 2006. [doi]

2005

An Evolutionary Algorithm for the Allocation Problem in High-level SynthesisHaidar M. Harmanani, Rony Saliba. jcsc, 14(2):347-366, 2005. [doi]

2004

A Parallel Genetic Algorithm For The Geometrically Constrained Site Layout Problem With Unequal-Size FacilitiesHaidar M. Harmanani, Pierrette Zouein, Aouni M. Hajar. ijcia, 4(4):375-400, 2004. [doi]

2003

A neural networks algorithm for data path synthesisHaidar M. Harmanani. cee, 29(4):535-551, 2003. [doi]

2002

A Parallel Neural Networks Algorithm for the Clique Partitioning ProblemHaidar M. Harmanani. isca, 9(2):83-89, 2002.

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