Shigeru Oyanagi - researchr alias

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Viewing Publication 1 - 24 from 24

2018

Underwater-Drone With Panoramic Camera for Automatic Fish Recognition Based on Deep LearningLin Meng, Takuma Hirayama, Shigeru Oyanagi. access, 6:17880-17886, 2018. [doi]

2017

The Development of Underwater-Drone equipped with 360-degree Panorama Camera in Opensource HardwareLin Meng, Takuma Hirayama, Shigeru Oyanagi. iiki 2018: 438-442 [doi]

2013

A Real-Time Burst Analysis MethodRyohei Ebina, Kenji Nakamura, Shigeru Oyanagi. ijait, 22(5), 2013. [doi]

2011

A Real-Time Burst Detection MethodRyohei Ebina, Kenji Nakamura, Shigeru Oyanagi. ictai 2011: 1040-1046 [doi]

An Improvement of Router Throughput for On-Chip Networks Using On-the-fly Virtual Channel AllocationSon Truong Nguyen, Shigeru Oyanagi. arcs 2011: 219-230 [doi]

An Input Buffer Architecture for On-chip RoutersChu Van Thiem, Shigeru Oyanagi. ic-nc 2011: 280-283 [doi]

2010

Control Independence Using Dual RenamingLin Meng, Shigeru Oyanagi. ic-nc 2010: 264-267 [doi]

A Low Cost Single-Cycle Router Based on Virtual Output Queuing for On-chip NetworksSon Truong Nguyen, Shigeru Oyanagi. dsd 2010: 60-67 [doi]

The Design of On-the-Fly Virtual Channel Allocation for Low Cost High Performance On-Chip RoutersSon Truong Nguyen, Shigeru Oyanagi. ic-nc 2010: 88-94 [doi]

2009

Pipelining a Multi-Mode SHA-384/512 Core with High Area Performance RateAnh Tuan Hoang, Katsuhiro Yamazaki, Shigeru Oyanagi. ieicet, 92-D(10):2034-2042, 2009. [doi]

2008

Multi-stage Pipelining MD5 Implementations on FPGA with Data ForwardingAnh Tuan Hoang, Katsuhiro Yamazaki, Shigeru Oyanagi. fccm 2008: 271-272 [doi]

Three-stage pipeline implementation for SHA2 using data forwardingAnh Tuan Hoang, Katsuhiro Yamazaki, Shigeru Oyanagi. fpl 2008: 29-34 [doi]

2006

Mining the K-Most Interesting Frequent Patterns SequentiallyTran Minh Quang, Shigeru Oyanagi, Katsuhiro Yamazaki. ideal 2006: 620-628 [doi]

ExMiner: An Efficient Algorithm for Mining Top-K Frequent PatternsTran Minh Quang, Shigeru Oyanagi, Katsuhiro Yamazaki. adma 2006: 436-447 [doi]

2004

Speculative Selection Routing in 2D Torus NetworkTran Cong So, Shigeru Oyanagi, Katsuhiro Yamazaki. ieicet, 87-D(7):1666-1673, 2004. [doi]

2002

Mining WWW Access Sequence by Matrix ClusteringShigeru Oyanagi, Kazuto Kubota, Akihiko Nakase. kdd 2003: 119-136 [doi]

2001

Implementation and performance evaluation of dynamic scheduling for parallel decision tree generationKazuto Kubota, Akihiko Nakase, Shigeru Oyanagi. ipps 2001: 157

1996

Improving the performance of global communication on a three-dimensional torus networkYasushi Kawakura, Noboru Tanabe, Shigeru Oyanagi. scjapan, 27(6):24-32, 1996. [doi]

1994

Improving the Performance of Global Communication on a 3D torus networkYasushi Kawakura, Shigeru Oyanagi. icpp 1994: 193-196

1992

Implementation of the prodigy parallel AI machine and performance evaluation of communicationNoboru Tanabe, Sadao Nakamura, Takashi Suzuoka, Shigeru Oyanagi. scjapan, 23(8):1-12, 1992. [doi]

1991

Base-m n-cube: High Performance Interconnection Networks for Highly Parallel Computer PRODIGYNoboru Tanabe, Takashi Suzuoka, Sadao Nakamura, Yasushi Kawakura, Shigeru Oyanagi. icpp 1991: 509-516

1989

Network Performance of the Prodigy Parallel AI MachineTakashi Suzuoka, Noboru Tanabe, Sadao Nakamura, Sumikazu Fujita, Shigeru Oyanagi. scjapan, 20(9):44-51, 1989. [doi]

1980

A Dynamically Microprogammable Computer with Low-Level ParallelismHiroshi Hagiwara, Shinji Tomita, Shigeru Oyanagi, Kiyoshi Shibayama. TC, 29(7):577-595, 1980.

1977

Hardware Organization of a Low Level Parallel ProcessorShinji Tomita, Kiyoshi Shibayama, Shigeru Oyanagi, Hiroshi Hagiwara. ifip11-9 1977: 855-860

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