Journal: VLSI Signal Processing

Volume 22, Issue 3

151 -- 162Efstathios D. Kyriakis-Bitzaros, Constantinos E. Goutis. A Space-Time Representation Method of Iterative Algorithms for the Design of Processor Arrays
163 -- 172Arda Yurdakul, Günhan Dündar. Multiplierless Realization of Linear DSP Transforms by Using Common Two-Term Expressions
173 -- 195S. Ramanathan, V. Visvanathan, S. K. Nandy. Architectural Synthesis of Computational Engines for Subband Adaptive Filtering
197 -- 215Eric Senn, Bertrand Zavidovique. Hazard-Free Self-Timed Design: Methodology and Application to Asynchronous Routing in an Heterogeneous Parallel Machine

Volume 22, Issue 2

83 -- 85Tuna B. Tarim, Robert L. Ewing. Editorial
87 -- 102Tuna B. Tarim, H. Hakan Kuntman, Mohammed Ismail. Robust Design of Basic Low Voltage CMOS Transconductors
103 -- 111Jing Xu, Raymond E. Siferd, Robert L. Ewing. High Performance CMOS Analog Arithmetic Circuits
113 -- 121Shenggao Li, Brian Okoon, Mona Hella, Mohammed Ismail, Maya Rubeiz. The Implementation of a VHDL-AMS to SPICE Converter
123 -- 134Robert L. Ewing. Technology Road Map to Methodologies for Mixed-Signal System Design and Simulation
135 -- 146Dennis Gibson, Carla N. Purdy. Extracting Behavioral Data from Physical Descriptions of MEMS for Simulation

Volume 22, Issue 1

5 -- 6Mohammad Ibrahim, Peter Pirsch, Johan McCanny. Guest Editors Introduction
9 -- 20Paul Lieverse, Ed F. Deprettere, Bart Kienhuis, Erwin A. de Kock. A Clustering Approach to Explore Grain-Sizes in the Definition of Processing Elements in Dataflow Architectures
21 -- 29Adel Baganne, Jean Luc Philippe, Eric Martin. A Co-Design Methodology for Telecommunication Systems: A Case Study of an Acoustic Echo Canceller
31 -- 43Mladen Berekovic, Helge Kloos, Peter Pirsch. Hardware Realization of a Java Virtual Machine for High Performance Multimedia Applications
45 -- 57Chidamber Kulkarni, Dennis Moolenaar, Lode Nachtergaele, Francky Catthoor, Hugo De Man. System-Level Energy-Delay Exploration for Multimedia Applications on Embedded Cores with Hardware Cache
59 -- 64Yoichi Katayama, Toshiaki Kitsuki, Yasushi Ooi. A Block Processing Unit in a Single-Chip MPEG-2 Video Encoder LSI
65 -- 75Benjamin Bishop, Thomas P. Kelliher, Robert Michael Owens, Mary Jane Irwin. Aggressive Dynamic Execution of Decoded Traces