113 | -- | 0 | Takao Nishitani, Peng H. Ang, Francky Catthoor. Introduction |
115 | -- | 120 | Tatsuo Ishiguro. VLSI in picture coding |
121 | -- | 131 | Robert Forchheimer, Keping Chen, Christer Svensson, Anders Ödmark. Single-chip image sensors with a digital processor array |
133 | -- | 140 | Hiroyuki Nakahira, Masakatsu Maruyama, Hideshi Ueda, Haruyasu Yamada. An image processing system using Image Signal Multiprocessors (ISMPs) |
141 | -- | 150 | Peter A. Ruetz, Po Tong, Daniel Luthi, Peng H. Ang. A video-rate JPEG chip set |
151 | -- | 158 | Takashi Miyazaki, Takao Nishitani, Masato Edahiro, Ikuko Ono, Kaoru Mitsuhashi. DCT/IDCT processor for HDTV developed with dsp silicon compiler |
159 | -- | 169 | Klaus Gaedke, Hartwig Jeschke, Peter Pirsch. A VLSI based MIMD architecture of a multiprocessor system for real-time video processing applications |
171 | -- | 184 | Marc Engels, Rudy Lauwereins, J. A. Peperstraete, Arthur H. M. van Roermund. Design of a processing board for a programmable multi-VSP system |
185 | -- | 199 | Ji-chien Lee, Bing J. Sheu, Rama Chellappa. A VLSI neuroprocessor for image restoration using analog computing-based systolic architecture |
201 | -- | 220 | Jef L. van Meerbergen, Paul E. R. Lippens, B. T. McSweeney, Wim F. J. Verhaegh, Albert van der Werf, A. van Zanten. Architectural strategies for high-throughput applications |
221 | -- | 235 | Toon Gijbels, Francky Catthoor, Luc Van Eycken, André Oosterlinck, Hugo De Man. An application-specific architecture for the RBN-coder with efficient memory organization |
237 | -- | 248 | C. V. Reventlow, M. Talmi, S. Wolf, M. Ernst, K. Müller, C. Stoffers. System considerations and the system level design of a chip set for real-time TV and HDTV motion estimation |
249 | -- | 259 | Ravi K. Kolagotla, Shu-sun Yu, Joseph JáJá. Systolic architectures for finite-state vector quantization |
261 | -- | 272 | Robert L. Stevenson, George B. Adams, Leah H. Jamieson, Edward J. Delp. Parallel implementation for iterative image restoration algorithms on a parallel DSP machine |
273 | -- | 282 | Frederico Buchholz Maciel, Yoshikazu Miyanaga, Koji Tochinai. An optimization technique for lowering the iteration bound of DSP programs |