Journal: VLSI Signal Processing

Volume 5, Issue 2-3

113 -- 0Takao Nishitani, Peng H. Ang, Francky Catthoor. Introduction
115 -- 120Tatsuo Ishiguro. VLSI in picture coding
121 -- 131Robert Forchheimer, Keping Chen, Christer Svensson, Anders Ödmark. Single-chip image sensors with a digital processor array
133 -- 140Hiroyuki Nakahira, Masakatsu Maruyama, Hideshi Ueda, Haruyasu Yamada. An image processing system using Image Signal Multiprocessors (ISMPs)
141 -- 150Peter A. Ruetz, Po Tong, Daniel Luthi, Peng H. Ang. A video-rate JPEG chip set
151 -- 158Takashi Miyazaki, Takao Nishitani, Masato Edahiro, Ikuko Ono, Kaoru Mitsuhashi. DCT/IDCT processor for HDTV developed with dsp silicon compiler
159 -- 169Klaus Gaedke, Hartwig Jeschke, Peter Pirsch. A VLSI based MIMD architecture of a multiprocessor system for real-time video processing applications
171 -- 184Marc Engels, Rudy Lauwereins, J. A. Peperstraete, Arthur H. M. van Roermund. Design of a processing board for a programmable multi-VSP system
185 -- 199Ji-chien Lee, Bing J. Sheu, Rama Chellappa. A VLSI neuroprocessor for image restoration using analog computing-based systolic architecture
201 -- 220Jef L. van Meerbergen, Paul E. R. Lippens, B. T. McSweeney, Wim F. J. Verhaegh, Albert van der Werf, A. van Zanten. Architectural strategies for high-throughput applications
221 -- 235Toon Gijbels, Francky Catthoor, Luc Van Eycken, André Oosterlinck, Hugo De Man. An application-specific architecture for the RBN-coder with efficient memory organization
237 -- 248C. V. Reventlow, M. Talmi, S. Wolf, M. Ernst, K. Müller, C. Stoffers. System considerations and the system level design of a chip set for real-time TV and HDTV motion estimation
249 -- 259Ravi K. Kolagotla, Shu-sun Yu, Joseph JáJá. Systolic architectures for finite-state vector quantization
261 -- 272Robert L. Stevenson, George B. Adams, Leah H. Jamieson, Edward J. Delp. Parallel implementation for iterative image restoration algorithms on a parallel DSP machine
273 -- 282Frederico Buchholz Maciel, Yoshikazu Miyanaga, Koji Tochinai. An optimization technique for lowering the iteration bound of DSP programs

Volume 5, Issue 1

6 -- 0Tomás Lang, Jaime H. Moreno. Introduction
21 -- 35Jens Franzen. A design method for on-line reconfigurable array processors
37 -- 47V. Hecht, Karsten Rönner, Peter Pirsch. A defect-tolerant systolic array implementation for real time image processing
49 -- 55J. L. Hueso, Gloria Martínez, Gloria Hernández. A systolic algorithm for the triangular Stein equation
57 -- 74Mohammed Ahmed Ghouse. 2D grid architectures for the DFT and the 2D DFT
75 -- 83Ross Smith, Gerald E. Sobelman, George Luk, Koichi Suda, Jeff Bracken. A programmable floating-point cell for systolic signal processing
85 -- 94Robert Cypher, C. Bernard Shung. Generalized trace-back techniques for survivor memory management in the Viterbi algorithm
95 -- 104J. Canaris. A VLSI architecture for the real time computation of discrete trigonometric transforms