Modeling VHDL in Multiclock ESTEREL

Basant Rajan, R. K. Shyamasundar. Modeling VHDL in Multiclock ESTEREL. In 13th International Conference on VLSI Design (VLSI Design 2000), 4-7 January 2000, Calcutta, India. pages 76-83, IEEE Computer Society, 2000. [doi]

Abstract

Abstract is missing.