Abstract is missing.
- Division Unit for Binary Integer DecimalsTomás Lang, Alberto Nannarelli. 1-7 [doi]
- A Combined Decimal and Binary Floating-Point MultiplierCharles Tsen, Sonia Gonzalez-Navarro, Michael J. Schulte, Brian J. Hickmann, Katherine Compton. 8-15 [doi]
- Parallel Prefix Ling Structures for Modulo 2^n-1 AdditionJun Chen, James E. Stine. 16-23 [doi]
- A FPGA-based Parallel Architecture for Scalable High-Speed Packet ClassificationWeirong Jiang, Viktor K. Prasanna. 24-31 [doi]
- Implementing a Highly Parameterized Digital PIV System on Reconfigurable HardwareAbderrahmane Bennis, Miriam Leeser, Gilead Tadmor. 32-37 [doi]
- Improving VLIW Processor Performance Using Three-Dimensional (3D) DRAM StackingYangyang Pan, Tong Zhang. 38-45 [doi]
- Specialization of the Cell SPE for Media ApplicationsCor Meenderinck, Ben H. H. Juurlink. 46-52 [doi]
- A Massively Parallel Coprocessor for Convolutional Neural NetworksMurugan Sankaradass, Venkata Jakkula, Srihari Cadambi, Srimat T. Chakradhar, Igor Durdanovic, Eric Cosatto, Hans Peter Graf. 53-60 [doi]
- An FPGA-based Parallel Hardware Architecture for Real-Time Face Detection Using a Face Certainty MapSeunghun Jin, Dongkyun Kim, Thuy Tuong Nguyen, Bongjin Jun, Daijin Kim, Jae Wook Jeon. 61-66 [doi]
- Accelerating a Virtual Ecology Model with FPGAsJulien Lamoureux, Tony Field, Wayne Luk. 67-74 [doi]
- Parallelized Architecture of Multiple Classifiers for Face DetectionJunguk Cho, Bridget Benson, Shahnam Mirzaei, Ryan Kastner. 75-82 [doi]
- Design and Implementation of a Radix-4 Complex Division Unit with PrescalingPouya Dormiani, Milos D. Ercegovac, Jean-Michel Muller. 83-90 [doi]
- A Low Power High Performance Radix-4 Approximate Squaring CircuitSatyendra R. Datla, Mitchell A. Thornton, David W. Matula. 91-97 [doi]
- A Novel Processor Architecture for McEliece Cryptosystem and FPGA PlatformsAbdulhadi Shoufan, Thorsten Wink, H. Gregor Molter, Sorin A. Huss, Falko Strenzke. 98-105 [doi]
- An Input Triggered Polymorphic ASIC for H.264 DecodingAdarsha Rao, Mythri Alle, Sainath V, Reyaz Shaik, Rajashekhar Chowhan, S. Sankaraiah, Sravanthi Mantha, S. K. Nandy, Ranjani Narayan. 106-113 [doi]
- A Power-Scalable Switch-Based Multi-processor FFTBassam Jamil Mohd, Earl E. Swartzlander Jr.. 114-120 [doi]
- MSA-CUDA: Multiple Sequence Alignment on Graphics Processing Units with CUDAYongchao Liu, Bertil Schmidt, Douglas L. Maskell. 121-128 [doi]
- Parallel Discrete Event Simulation of Molecular Dynamics Through Event-Based DecompositionMartin C. Herbordt, Md. Ashfaquzzaman Khan, Tony Dean. 129-136 [doi]
- NeMo: A Platform for Neural Modelling of Spiking Neurons Using GPUsAndreas Fidjeland, Etienne B. Roesch, Murray Shanahan, Wayne Luk. 137-144 [doi]
- Constraint-Driven Instructions Selection and Application Scheduling in the DURASE systemKevin Martin, Christophe Wolinski, Krzysztof Kuchcinski, Antoine Floch, François Charot. 145-152 [doi]
- A System Framework for the Design of Embedded Software Targeting Heterogeneous Multi-core SoCsXavier Guerin, Frédéric Pétrot. 153-160 [doi]
- Impact of Loop Tiling on the Controller Logic of Acceleration EnginesHritam Dutta, Jiali Zhai, Frank Hannig, Jürgen Teich. 161-168 [doi]
- Evaluating Various Branch-Prediction Schemes for Biomedical-Implant ProcessorsChristos Strydis, Georgi Gaydadjiev. 169-176 [doi]
- Low-Power ASIP Architecture Exploration and Optimization for Reed-Solomon ProcessingAndreas Genser, Christian Bachmann, Christian Steger, Jos Hulzink, Mladen Berekovic. 177-182 [doi]
- Scalar Processing Overhead on SIMD-Only ArchitecturesArnaldo Azevedo Filho, Ben H. H. Juurlink. 183-190 [doi]
- Integral Parallel Architecture & Berkeley s MotifsMihaela Malita, Gheorghe Stefan. 191-194 [doi]
- Application Specific Transistor Sizing for Low Power Full AddersFatemeh Eslami, Amirali Baniasadi, Mostafa Farahani. 195-198 [doi]
- Reconfigurable SWP Operator for Multimedia ProcessingShafqat Khan, Emmanuel Casseau, Daniel Menard. 199-202 [doi]
- Filtering Global History: Power and Performance Efficient Branch PredictorRaid Ayoub, Alex Orailoglu. 203-206 [doi]
- Efficient Implementation of Carry-Save Adders in FPGAsJavier Hormigo, Manuel Ortiz, Francisco J. Quiles, Francisco J. Jaime, Julio Villalba, Emilio L. Zapata. 207-210 [doi]
- Acceleration of Multiresolution Imaging Algorithms: A Comparative StudyRichard Membarth, Philipp Kutzer, Hritam Dutta, Frank Hannig, Jürgen Teich. 211-214 [doi]
- A High-Performance Hardware Architecture for Spectral Hash AlgorithmRay C. C. Cheung, Çetin K. Koç, John D. Villasenor. 215-218 [doi]
- P3FSM: Portable Predictive Pattern Matching Finite State MachineLucas Vespa, Mini Mathew, Ning Weng. 219-222 [doi]
- Run-Time Detection of Malwares via Dynamic Control-Flow InspectionYong-Joon Park, Zhao Zhang, Songqing Chen. 223-226 [doi]
- A 16-context Optically Reconfigurable Gate ArrayMao Nakajima, Minoru Watanabe. 227-230 [doi]
- Mapping Parallel FFT Algorithm onto SmartCell Coarse-Grained Reconfigurable ArchitectureCao Liang, Xin-Ming Huang. 231-234 [doi]
- An Area-Efficient LDPC Decoder Architecture and Implementation for CMMB SystemsKai Zhang, Xinming Huang, Zhongfeng Wang. 235-238 [doi]