Abstract is missing.
- Message from the conference chairs [doi]
- Era of customization and specializationJason Cong. 3 [doi]
- More than 50 years of parallel processing and still no easy path to speedupMichael Flynn. 4 [doi]
- Architectures for Green routersViktor K. Prasanna. 5 [doi]
- CusComNet: A customisable network for reconfigurable heterogeneous clustersStewart Denholm, Kuen Hung Tsoi, Peter Pietzuch, Wayne Luk. 9-16 [doi]
- Address generation scheme for a coarse grain reconfigurable architectureMuhammad Ali Shami, Ahmed Hemani. 17-24 [doi]
- Accelerating vision and navigation applications on a customizable platformJason Cong, Beayna Grigorian, Glenn Reinman, Marco Vitanza. 25-32 [doi]
- A high-performance, low-power linear algebra coreArdavan Pedram, Andreas Gerstlauer, Robert A. van de Geijn. 35-42 [doi]
- A decimal floating-point fused multiply-add unit with a novel decimal leading-zero anticipatorAhmet Akkas, Michael J. Schulte. 43-50 [doi]
- Longest Prefix Match and updates in Range TriesIoannis Sourdis, Sri Harsha Katamaneni. 51-58 [doi]
- Low-cost hardware profiling of run-time and energy in FPGA embedded processorsMark Aldham, Jason Helge Anderson, Stephen Dean Brown, Andrew Canis. 61-68 [doi]
- TimeTrial: A low-impact performance profiler for streaming data applicationsJoseph M. Lancaster, E. F. Berkley Shands, Jeremy D. Buhler, Roger D. Chamberlain. 69-76 [doi]
- System-level design space exploration for dedicated heterogeneous multi-processor systemsLuigi Pomante. 79-86 [doi]
- Decentralized dynamic resource management support for massively parallel processor arraysVahid Lari, Andriy Narovlyanskyy, Frank Hannig, Jürgen Teich. 87-94 [doi]
- Hybrid data structure for IP lookup in virtual routers using FPGAsOguzhan Erdem, Hoang Le, Viktor K. Prasanna, Cüneyt F. Bazlamaçci. 95-102 [doi]
- An area-Efficient LDPC decoder for multi-standard with conflict resolutionChangsheng Zhou, Yunlong Ge, Xubin Chen, Yun Chen, Xiaoyang Zeng. 105-112 [doi]
- High-throughput Contention-Free concurrent interleaver architecture for multi-standard turbo decoderGuohui Wang, Yang Sun, Joseph R. Cavallaro, Yuanbin Guo. 113-121 [doi]
- Energy-efficient floating-point arithmetic for software-defined radio architecturesSyed Zohaib Gilani, Nam Sung Kim, Michael J. Schulte. 122-129 [doi]
- On the performance of GPU public-key cryptographySamuel Neves, Filipe Araujo. 133-140 [doi]
- Exploiting structural redundancy of SIMD accelerators for their built-in self-testing/diagnosis and reconfigurationAlessandro Strano, Davide Bertozzi, Arnaud Grasset, Sami Yehia. 141-148 [doi]
- Accelerating the photon mapping algorithm and its hardware implementationShawn Singh, Seung hyun Pan, Milos Ercegovac. 149-157 [doi]
- A low power fault-tolerance architecture for the kernel density estimation based image segmentation algorithmPeng Li, David J. Lilja. 161-168 [doi]
- Instruction set extension for high throughput disparity estimation in stereo image processingChristian Banz, Carsten Dolar, Fabian Cholewa, Holger Blume. 169-175 [doi]
- Low energy motion estimation via selective aproximationsYunus Emre, Chaitali Chakrabarti. 176-183 [doi]
- An FPGA architecture for solving the Table Maker's DilemmaFlorent de Dinechin, Jean-Michel Muller, Bogdan Pasca, Alexandru Plesco. 187-194 [doi]
- Next-generation massively parallel short-read mapping on FPGAsOliver Knodel, Thomas B. Preußer, Rainer G. Spallek. 195-201 [doi]
- An FPGA-based real-time nonuniformity correction system for Infrared Focal Plane ArraysRodolfo Redlich, Gonzalo Carvajal, Miguel Figueroa. 202-208 [doi]
- Efficient custom instruction enumeration for extensible processorsChenglong Xiao, Emmanuel Casseau. 211-214 [doi]
- IP-XACT extensions for Reconfigurable ComputingRazvan Nane, Sven van Haastregt, Todor Stefanov, Bart Kienhuis, Vlad Mihai Sima, Koen Bertels. 215-218 [doi]
- An integrated development toolset and implementation methodology for partially reconfigurable system-on-chipsAbelardo Jara-Berrocal, Ann Gordon-Ross. 219-222 [doi]
- Cooperative multitasking for heterogeneous accelerators in the Linux Completely Fair SchedulerTobias Beisel, Tobias Wiersema, Christian Plessl, André Brinkmann. 223-226 [doi]
- Optimal design-space exploration of streaming applicationsShobana Padmanabhan, Yixin Chen, Roger D. Chamberlain. 227-230 [doi]
- Stack data management for Limited Local Memory (LLM) multi-core processorsKe Bai, Aviral Shrivastava, Saleel Kudchadker. 231-234 [doi]
- An energy efficient adaptive event detection scheme for wireless sensor networkZheng Zhou, Gang Qu. 235-238 [doi]
- Architecture model for approximate tandem repeat detectionTomás Martínek, Matej Lexa. 239-242 [doi]
- Design of a high performance FPGA based fault injector for real-time safety-critical systemsMarko Miklo, Carl R. Elks, Ronald D. Williams. 243-246 [doi]
- Domain-specific processor with 3D integration for medical image processingJason Cong, Karthik Gururaj, Muhuan Huang, Sen Li, Bingjun Xiao, Yi Zou. 247-250 [doi]
- A parallel k-partition method to perform Montgomery MultiplicationJoão Carlos Néto, Alexandre F. Tenca, Wilson Vicente Ruggiero. 251-254 [doi]
- A Residue Logarithmic Number System ALU using interpolation and cotransformationMark G. Arnold, Ioannis Kouretas, Vassilis Paliouras. 255-258 [doi]
- Design and implementation of a belief propagation detector for sparse channelsYanjie Peng, Kai Zhang, Andrew G. Klein, Xinming Huang. 259-262 [doi]