Abstract is missing.
- Embedded market: challenges and opportunitiesVida Ilderem. 1-2 [doi]
- Rank based dynamic voltage and frequency scaling fortiled graphics processorsB. V. N. Silpa, Gummidipudi Krishnaiah, Preeti Ranjan Panda. 3-12 [doi]
- Intermediate fabrics: virtual architectures for circuit portability and fast placement and routingJames Coole, Greg Stitt. 13-22 [doi]
- An elastic software cache with fast prefetching for motion compensation in video decodingPing Chao, Youn-Long Lin. 23-32 [doi]
- Verification of dynamically reconfigurable embedded systems by model transformation rulesFelix Madlener, Julia Weingart, Sorin A. Huss. 33-40 [doi]
- Hardware/software optimization of error detection implementation for real-time embedded systemsAdrian Lifa, Petru Eles, Zebo Peng, Viacheslav Izosimov. 41-50 [doi]
- Scheduling garbage collection in real-time systemsMartin Kero, Simon Aittamaa. 51-60 [doi]
- From ESL 2010 to ESL 2015Tor E. Jeremiassen, Tim Kogel, Andrés Takach, Grant Martin, Adam Donlin, Karamvir Chatha. 61-62 [doi]
- Hardware/software co-design for high performance computing: challenges and opportunitiesXiaobo Sharon Hu, Richard C. Murphy, Sudip S. Dosanjh, Kunle Olukotun, Stephen Poole. 63-64 [doi]
- Exploring programming model-driven QoS support for NoC-based platformsJaume Joven, Andrea Marongiu, Federico Angiolini, Luca Benini, Giovanni De Micheli. 65-74 [doi]
- Optimal synthesis of latency and throughput constrained pipelined MPSoCs targeting streaming applicationsHaris Javaid, Xin He, Aleksandar Ignjatovic, Sri Parameswaran. 75-84 [doi]
- OE+IOE: a novel turn model based fault tolerant routing scheme for networks-on-chipSudeep Pasricha, Yong Zou, Dan Connors, Howard Jay Siegel. 85-94 [doi]
- Power aware SID-based simulator for embedded multicore DSP subsystemsCheng-Yen Lin, Po-Yu Chen, Chun-Kai Tseng, Chung-Wen Huang, Chia-Chieh Weng, Chi-Bang Kuan, Shih-Han Lin, Shi-Yu Huang, Jenq Kuen Lee. 95-104 [doi]
- Accurate online power estimation and automatic battery behavior based power model generation for smartphonesLide Zhang, Birjodh Tiwana, Zhiyun Qian, Zhaoguang Wang, Robert P. Dick, Zhuoqing Morley Mao, Lei Yang. 105-114 [doi]
- Statistical approach in a system level methodology to deal with process variationConcepción Sanz Pineda, Manuel Prieto, José Ignacio Gómez, Christian Tenllado, Francky Catthoor. 115-124 [doi]
- Worst-case performance analysis of synchronous dataflow scenariosMarc Geilen, Sander Stuijk. 125-134 [doi]
- Improving platform-based system synthesis by satisfiability modulo theories solvingFelix Reimann, Michael Glaß, Christian Haubelt, Michael Eberl, Jürgen Teich. 135-144 [doi]
- A case for lifetime-aware task mapping in embedded chip multiprocessorsAdam S. Hartman, Donald E. Thomas, Brett H. Meyer. 145-154 [doi]
- Automatic memory partitioning: increasing memory parallelism via data structure partitioningYosi Ben-Asher, Nadav Rotem. 155-162 [doi]
- Towards a synthesis semantics for systemC channelsKim Grüttner, Henning Kleen, Frank Oppenheimer, Achim Rettberg, Wolfgang Nebel. 163-172 [doi]
- Demand-based block-level address mapping in large-scale NAND flash storage systemsZhiwei Qin, Yi Wang, Duo Liu, Zili Shao. 173-182 [doi]
- An introduction to the SystemC synthesis subset standardPhilippe Coussy, Andrés Takach, Michael McNamara, Mike Meredith. 183-184 [doi]
- Compilation techniques for CGRAs: exploring all parallelization approachesTom Vander Aa, Praveen Raghavan, Scott A. Mahlke, Bjorn De Sutter, Aviral Shrivastava, Frank Hannig. 185-186 [doi]
- Dynamic, non-linear cache architecture for power-sensitive mobile processorsGaro Bournoutian, Alex Orailoglu. 187-194 [doi]
- A greedy buffer allocation algorithm for power-aware communication in body sensor networksHassan Ghasemzadeh, Roozbeh Jafari. 195-204 [doi]
- High durability in NAND flash memory through effective page reuse mechanismsKwangyoon Lee, Alex Orailoglu. 205-212 [doi]
- A holistic approach to network-on-chip synthesisGlenn Leary, Karam S. Chatha. 213-222 [doi]
- NeuroNoC: neural network inspired runtime adaptation for an on-chip communication architectureThomas Ebi, Mohammad Abdullah Al Faruque, Jörg Henkel. 223-230 [doi]
- Workload characterization and its impact on multicore platform designPaul Bogdan, Radu Marculescu. 231-240 [doi]
- parSC: synchronous parallel systemc simulation on multi-core host architecturesChristoph Schumacher, Rainer Leupers, Dietmar Petras, Andreas Hoffmann. 241-246 [doi]
- FastFwd: an efficient hardware acceleration technique for trace-driven network-on-chip simulationGummidipudi Krishnaiah, B. V. N. Silpa, Preeti Ranjan Panda, Anshul Kumar. 247-256 [doi]
- FEMU: a firmware-based emulation framework for SoC verificationHao Li, Dong Tong, Kan Huang, Xu Cheng. 257-266 [doi]
- Automatic parallelization of embedded software using hierarchical task graphs and integer linear programmingDaniel Cordes, Peter Marwedel, Arindam Mallik. 267-276 [doi]
- Performance modeling of embedded applications with zero architectural knowledgeMarco Lattuada, Fabrizio Ferrandi. 277-286 [doi]
- A performance model and code overlay generator for scratchpad enhanced embedded processorsMichael A. Baker, Amrit Panda, Nikhil Ghadge, Aniruddha Kadne, Karam S. Chatha. 287-296 [doi]
- System-level reliability modeling for MPSoCsYun Xiang, Thidapat Chantem, Robert P. Dick, Xiaobo Sharon Hu, Li Shang. 297-306 [doi]
- A task remapping technique for reliable multi-core embedded systemsChanhee Lee, Hokeun Kim, Hae-woo Park, Sungchan Kim, Hyunok Oh, Soonhoi Ha. 307-316 [doi]
- Heap data management for limited local memory (LLM) multi-core processorsKe Bai, Aviral Shrivastava. 317-326 [doi]
- Unconventional fabrics, architectures, and models for future multi-core systemsRadu Marculescu, Christof Teuscher, Partha Pratim Pande. 327-328 [doi]
- Modeling and analyzing real-time multiprocessor systemsMaarten Wiggers, Lothar Thiele, Edward A. Lee, Simon Schliecker, Marco Bekooij. 329-330 [doi]
- Exploring models of computation with ptolemy IIChristopher X. Brooks, Edward A. Lee, Stavros Tripakis. 331-332 [doi]