Abstract is missing.
- A wearable human activity recognition system on a chipKoldo Basterretxea, Javier Echanobe, Inés del Campo. 1-8 [doi]
- Hardware architecture design and implementation for FMCW radar signal processing algorithmEugin Hyun, Jonghun Lee. 1-6 [doi]
- PHAT: A technology for prototyping parallel heterogeneous architecturesThorsten Wink, Andreas Koch 0001. 1-8 [doi]
- Closed-loop adaptive and stochastic prefetch mechanism for data arrayLionel Vincent, Stéphane Mancini. 1-8 [doi]
- FPGA implementation of a flexible synchronizer for cognitive radio applicationsFarid Shamani, Roberto Airoldi, Tapani Ahonen, Jari Nurmi. 1-8 [doi]
- Flexible real-time transmitter at 10 Gbit/s for SCFDMA PONs focusing on low-cost ONUsLukas Meder, Philipp C. Schindler, A. Agmon, M. Meltsin, R. Bonk, Joachim Meyer, Michael Dreschmann, Alex Tolmachev, R. Hilgendorf, Moshe Nazarathy, Shalva Ben-Ezra, T. Pfeiffer, Wolfgang Freude, Juerg Leuthold, Christian Koos, Jürgen Becker. 1-8 [doi]
- Hardware-software implementation of vehicle detection and counting using virtual detection linesTomasz Kryjak, Mateusz Komorkiewicz, Marek Gorgon. 1-8 [doi]
- Optimizing memory bandwidth in OpenVX graph execution on embedded many-core acceleratorsGiuseppe Tagliavini, Germain Haugou, Luca Benini. 1-8 [doi]
- Model-driven design flow for distributed control in reconfigurable FPGA systemsChiraz Trabelsi, Samy Meftali, Rabie Ben Atitallah, Jean-Luc Dekeyser. 1-6 [doi]
- Toward the synthesis of fixed-point code for matrix inversion based on Cholesky decompositionMatthieu Martel, Amine Najahi, Guillaume Revy. 1-8 [doi]
- TURNUS: An open-source design space exploration framework for dynamic stream programsSimone Casale Brunet, M. Wiszniewska, Endri Bezati, Marco Mattavelli, Jörn W. Janneck, Massimo Canale. 1-2 [doi]
- Self-adaptive harris corner detector on heterogeneous many-core processorJohny Paul, Walter Stechele, Ericles Rodrigues Sousa, Vahid Lari, Frank Hannig, Jürgen Teich, Manfred Kröhnert, Tamim Asfour. 1-8 [doi]
- A framework for rapid prototyping of embedded vision applicationsMichael Mefenza, Franck Yonga, Luca Bochi Saldanha, Christophe Bobda, Senem Velipasalar. 1-8 [doi]
- Execution trace graph analysis of dataflow programs: Bounded buffer scheduling and deadlock recovery using model predictive controlSimone Casale Brunet, Endri Bezati, Marco Mattavelli, Massimo Canale, Jörn W. Janneck. 1-6 [doi]
- Video++, a modern image and video processing C++ frameworkMatthieu Garrigues, Antoine Manzanera. 1-6 [doi]
- Robust unclonable identifiers and true random numbers from off-the-shelf SRAMsMiguel A. Prada-Delgado, Susana Eiroa, Iluminada Baturone. 1-2 [doi]
- Hardware realization of an FPGA processor - Operating system call offload and experiencesAndreas Erik Hindborg, Pascal Schleuniger, Nicklas Bo Jensen, Sven Karlsson. 1-8 [doi]
- A fast method for overflow effect analysis in fixed-point systemsR. Nehmeh, Daniel Menard, Andrei Banciu, Thierry Michel, Romuald Rocher. 1-6 [doi]
- MARTE to ΠSDF transformation for data-intensive applications analysisManel Ammar, Mouna Baklouti, Maxime Pelcat, Karol Desnos, Mohamed Abid. 1-8 [doi]
- Communication-model based embedded mapping of dataflow actors on heterogeneous MPSoCThanh Dinh Ngo, Daniel Sepulveda, Kevin J. M. Martin, Jean-Philippe Diguet. 1-8 [doi]
- HLS-based FPGA implementation of a predictive block-based motion estimation algorithm - A field reportGregor Schewior, Christian Zahl, Holger Blume, Stefan Wonneberger, Jan Effertz. 1-8 [doi]
- CUVLE: Variable-length encoding on CUDAAntonio Fuentes-Alventosa, Juan Gómez-Luna, José María González-Linares, Nicolás Guil Mata. 1-6 [doi]
- Energy-aware decoders: A case study based on an RVC-CAL specificationRong Ren, E. Juárez, César Sanz, Mickaël Raulet, Fernando Pescador. 1-6 [doi]
- Foreground detection in video streams in an FPGA without external memoryMartin Danek, Roman Bartosinski, Christian Hochberger. 1-6 [doi]
- A scalable hardware architecture for retinal blood vessel detection in high resolution fundus imagesHamza Bendaoudi, Farida Cheriet, Houssem Ben Tahar, J. M. Pierre Langlois. 1-6 [doi]
- Energy efficiency and performance management of parallel dataflow applicationsSimon Holmbacka, Erwan Nogues, Maxime Pelcat, Sébastien Lafond, Johan Lilius. 1-8 [doi]
- Hardware implementation of a biometric recognition algorithm based on in-air signatureRosario Arjona, Rocio Romero-Moreno, Iluminada Baturone. 1-6 [doi]
- Optimized fixed point implementation of a local stereo matching algorithm onto C66x DSPJudicael Menant, Muriel Pressigout, Luce Morin, Jean-François Nezan. 1-6 [doi]
- 0, 1, 2, many - A classroom occupancy monitoring system for smart public buildingsFrancesco Paci, Davide Brunelli, Luca Benini. 1-6 [doi]
- Automatic generation of dataflow-based reconfigurable co-processing unitsCarlo Sau, Francesca Palumbo. 1-8 [doi]
- Energy consumption modeling of smart nodes with a function approachAina Randrianarisaina, Olivier Pasquier, Pascal Chargé. 1-6 [doi]
- A review of world's fastest connected component labeling algorithms: Speed and energy estimationLaurent Cabaret, Lionel Lacassagne, Louiza Oudni. 1-6 [doi]
- Accelerating local feature extraction using OpenCL on heterogeneous platformsKonrad Moren, Thomas Perschke, Diana Göhringer. 1-8 [doi]
- Low-cost guaranteed-throughput dual-ring communication infrastructure for heterogeneous MPSoCsBerend H. J. Dekens, Philip S. Wilmanns, Gerard J. M. Smit, Marco Bekooij. 1-8 [doi]
- Demonstrating a dataflow-based RTOS for heterogeneous MPSoC by means of a stereo matching applicationJulien Heulot, Judicael Menant, Maxime Pelcat, Jean-François Nezan, Luce Morin, Muriel Pressigout, Slaheddine Aridhi. 1-2 [doi]
- Synthilation: JIT-compilation of microinstruction sequences in AMIDAR processorsChristian Hochberger, Lukas Johannes Jung, Andreas Engel 0003, Andreas Koch 0001. 1-6 [doi]
- Orcc's compa-backend demonstrationYaset Oliva, Emmanuel Casseau, Kevin Martin, Pierre Bomel, Jean-Philippe Diguet, Hervé Yviquel, Mickaël Raulet, Erwan Raffin, Laurent Morin. 1-2 [doi]
- Rakeness-based compressed sensing on ultra-low power multi-core biomedicai processorsDaniele Bortolotti, Mauro Mangia, Andrea Bartolini, Riccardo Rovatti, Gianluca Setti, Luca Benini. 1-8 [doi]
- Demo nightTomasz Kryjak, Jorge Portilla. 1 [doi]