Abstract is missing.
- A VHDL-AMS library of hierarchical optoelectronic device modelsFabien Mieyeville, Matthieu Briere, Ian O Connor, Frédéric Gaffiot, Gilles Jacquemod. 7-19 [doi]
- Design and Modelling of an I2C Bus ControllerT. Cuenin, Olivier Romain, Patrick Garda. 19-31 [doi]
- A behavioural description with VHDL-AMS of a piezo-ceramic ultrasound transducer based on the Redwood s modelRachid Guelaz, Djilali Kourtiche, Mustapha Nadi. 32-44 [doi]
- SystemC - a powerful system-level modelling platform for digital and mixed-signal hardware/software co-designC. Isaia, Tom J. Kazmierski. 45-54 [doi]
- Analog Circuit Modeling in SystemCMassimo Conti, Marco Caldari, Simone Orcioni, Giorgio Biagetti. 54-65 [doi]
- Synchronization of analogue and digital solvers in mixed-signal simulation on a SystemC platformTom J. Kazmierski, Hessa Al-Junaid. 65-72 [doi]
- SystemC-AMS Steps towards an ImplementationKarsten Einwich, Peter Schwarz. 72-81 [doi]
- A New Method for Modeling and Analysis of Accuracy and Tolerances in Mixed-Signal SystemsWilhelm Heupke, Christoph Grimm, Klaus Waldschmidt. 82-90 [doi]
- Simple Models for Complex Systems : A-FSM TemplateYannick Hervé. 90-98 [doi]
- Rules for Analog and Mixed-Signal VHDL-AMS ModelingJ. Haase. 98-108 [doi]
- Modelling of transient noise sources with VHDL-AMS and normative spectral interpretationGuillaume Monnerie, Noëlle Lewis, Dominique Dallet, H. Levi, M. Robbe. 108-120 [doi]
- Description Languages and Tools for the Behavioural Simulation of SD Modulators: a Comparative SurveyR. Castro-López, José Manuel de la Rosa, R. Romay, Rocio del Río, Fernando Manuel Medeiro Hidalgo, F. Fernandez. 121-133 [doi]
- Towards High-Level Synthesis of Analog and Mixed-Signal Systems from VHDL-AMS SpecificationsAlex Doboli, Hua Tang, Hui Zhang. 133-141 [doi]
- VHDL-AMS Behavioural Modelling of a Switched Current Sigma-Delta ModulatorAhmed Fakhfakh, Mourad Loulou, N. Ksentini, Nouri Masmoudi, Jean-Jacques Charlot. 141-150 [doi]
- Hierarchical synthesis of high-speed CMOS photoreceiver front-ends using a multi-domain behavioural description languageFaress Tissafi-Drissi, Ian O Connor, F. Mieyeveville, Frédéric Gaffiot. 151-163 [doi]
- FIST - a VHDL-AMS based architectural synthesis strategy for integrated high-frequency analogue filtersFazrena A. Hamid, Tom J. Kazmierski. 163-175 [doi]
- Reliability simulation of electronic circuits with VHDL-AMSF. Marc, B. Mongellaz, Y. Danto. 175-184 [doi]
- Micromotor Simulation with VHDL-AMSJean Oudinot, G. Overton, Aitor Endemaño Isasi, Marc P. Y. Desmulliez, Jean-Yves Fourniols, Sylvaine Muratet. 185-197 [doi]
- A Seamless Simulink Based System Desing Flow for Automotive ApplicationsMartin Stark, Jan-Hendrik Oetjens, Wolfgang Rosenstiel. 197-204 [doi]
- VerilogAMS language used in the Top-Down Methodology for wireless integrated circuit designsA. F. Noullet, F. Healey, O. Tico, R. Santonja, J.-C. Mboli, T. Nouguier. 204-213 [doi]
- Towards a Conceptual Framework for UML to Hardware Description Language MappingsI. Oliver, M. Marchetti. 214-226 [doi]
- UML-based Specifications of an Embedded System oriented to HW/SW partitioning: a case studyA. Minosi, S. Mankan, A. Martinola, F. Balzarini, A. Kostadinov, Mauro Prevostini. 226-238 [doi]
- A UML Approach for Modeling the Components of a Test System for Integrated CircuitsC. Spircu, T. Gentnet, H. Beyer. 238-250 [doi]
- A Unified Approach to Code Generation from Behavioral DiagramsDag Björklund, Johan Lilius, Ivan Porres. 251-263 [doi]
- Generating JML Specifications from UML State DiagramsEngelbert Hubbers, Martijn Oostdijk. 263-274 [doi]
- Interoperability between Design and Simulation Tools using Model Transformation TechniquesCédric Dumoulin, Jean-Luc Dekeyser, Boris Kokoszko, S. Pulon, G. Cristau. 274-285 [doi]
- UML-Based Co-Design for Run-Time Reconfigurable ArchitecturesD. Fröhlich, B. Steinbach, Tilman Beierlein. 285-297 [doi]
- UML to XML-Schema Transformation: a Case Study in Managing Alternative Model Transformations in MDAIvan Kurtev, Klaas van den Berg, Mehmet Aksit. 297-309 [doi]
- MDA for SoC Design, Intensive Signal Processing ExperimentPierre Boulet, Jean-Luc Dekeyser, Cédric Dumoulin, Philippe Marquet. 309-317 [doi]
- Platform-independent Design for Embedded Real-time Systems Jinfeng Huang, Jeroen Voeten, Andre Ventevogel, Leo J. van Bokhoven. 318-330 [doi]
- Traversing the Fundamental System-Level Design Gap Using Modeling PatternsM. Verhappen, Jeroen Voeten, P. H. A. van der Putten. 330-342 [doi]
- Real-time system modeling with ACCORD/UML methodology: Illustration through an automotive case studyT. H. Phan, Sébastien Gérard, François Terrier. 342-354 [doi]
- From UML statecharts to FPGA - the HiCoS approachGrzegorz Labiak. 354-364
- Supporting Consistency Control between Functional and Structural Views in Interface-based Design ModelsLeandro Soares Indrusiak, R. Reis, Manfred Glesner. 364-373 [doi]
- Using Symbolic Simulation for Bounded Property CheckingJürgen Ruf, Prakash Mohan Peranandam, Thomas Kropf, Wolfgang Rosenstiel. 374-385 [doi]
- Exact Low-Level Runtime Analysis of Synchronous Programs for Formal Verification of Real-Time SystemsGeorge Logothetis, Klaus Schneider, C. Metzler. 385-405 [doi]
- Intuitive Representations for Temporal Logic FormulasY. Zhao. 405-414 [doi]
- Deadlock Analysis in StatechartsAndrei Karatkevich. 414-425 [doi]
- Formal Specification of a 40GBit/s Sonet/SDH ASICWerner Haas, T. Bürner, Stefan Gossens, Ulrich Heinkel. 426-435 [doi]
- Proof-based design of a microelectronic architecture for MPEG-2 bit-rate measurement Dominique Cansell, Dominique Méry, Cyril Proch. 435-447 [doi]
- A New Time Extension to phi-Calculus based on Time Consuming Transition SemanticsM. Fischer, André Windisch, Stefan Förster, B. Balser, Dieter Monjau. 447-456 [doi]
- TCTL-Based Verification of Industrial ProcessesA. Ayoub, Ayman M. Wahba, Ashraf M. Salem, Mohamed A. Sheirah. 456-468 [doi]
- Refinement of Hybrid Systems from Formal Models to Design LanguagesJ. Romberg, Christoph Grimm. 469-481 [doi]
- Modeling CHP descriptions in Labeled Transitions Systems for an efficient formal validation of asynchronous circuit specificationsDominique Borrione, Menouer Boubekeur. 481-492 [doi]
- Using Rewriting-Logic Notation for Funcional Verification in Data-Stream Based Reconfigurable ComputingMauricio Ayala-Rincón, Ricardo P. Jacobi, Carlos H. Llanos, Reiner W. Hartenstein. 492-504 [doi]
- Using UML-B and U2B for formal refinement of digital components1Colin F. Snook, Kim Sandström. 505-515 [doi]
- Combining Formal Refinement and Model Checking for Real-Time Systems VerificationAlexander Krupp, Wolfgang Müller 0003. 515-525 [doi]
- Process Algebraic Specification, Refinement, and Verification of Embedded SystemsStefan Förster, M. Fischer, Dieter Monjau, André Windisch, B. Balser. 525-536 [doi]
- Compositional Proof Rules for Hierarchical Timed AutomataJ. Fogel. 536-547 [doi]
- On Hardware Description in ECLLluís Ribas, Joaquín Saiz. 548-557 [doi]
- Software-Compiled System Desing: a methodology based approach to the specification & desing of Programmable SoCChris Sullivan, Jeff Jussel. 557-565 [doi]
- Modeling of CSP, KPN and SR Systems with SystemCFernando Herrera, Pablo Sánchez, Eugenio Villar. 572-583 [doi]
- A Graphical Tool for System-Level Modeling and Simulation with SystemCJean Paul Calvez, Rocco Le Moigne, Olivier Pasquier. 583-593 [doi]
- A Tool-Set for Table Based Direct Behavioral Configuration of C++ ModelsC. Jaeschke, B. Hoppe, W. Sauer. 593-605 [doi]
- Exploring Models of Computation through Static AnalysisI. Jeukens, M. Strum. 605-616 [doi]
- sciPROVE: C++ Based Verification Environment for IP and SoC Design1U. Badelt, H. Kühl, Martin Radetzki. 617-627 [doi]
- Case Study: SystemC-Based Design of an Industrial Exposure Control Unit1Axel Braun, Thorsten Schubert, Martin Stark, Karsten Haug, Joachim Gerlach, Wolfgang Rosenstiel. 627-636 [doi]
- Functional Verification Environment for Object-oriented Hardware DesignsA. Ziv. 637-646 [doi]
- Efficient Automatic Visualization of SystemC DesignsDaniel Große, Rolf Drechsler, Lothar Linhard, Gerhard Angst. 646-658 [doi]
- LAERTE++: an Object Oriented High-level TPG for SystemC DesignsAlessandro Fin, Franco Fummi. 658-668 [doi]
- An Internal Representation Model for System-Level Co-Design of Heterogeneous Multiprocessor Embedded SystemFabio Salice, William Fornaciari, Luigi Pomante, Donatella Sciuto. 669-680
- Object-Oriented ASIP Design and SynthesisMaziar Goudarzi, Shaahin Hessabi, Alan Mycroft. 680-692 [doi]
- Dynamic Power Management of an AMBA-based Platform in SystemCMassimo Conti, Marco Caldari, Simone Orcioni. 692-704 [doi]
- SPACE: A Hardware/Software SystemC Modeling Platform Including an RTOSJérôme Chevalier, Mathieu Rondonneau, Olivier Benny, Guy Bois, El Mostapha Aboulhamid, François R. Boyer. 704-716 [doi]
- C-model integration and software development using system-level simulation at TLM in a SystemC-based desing flowOle Blaurock. 716-719 [doi]
- Design and Power Analysis in SysteC of an I2C Bus DriverMarco Caldari, Massimo Conti, Paolo Crippa, Simone Orcioni, Claudio Turchetti. 719-727 [doi]
- Hardware Definition Based on Standard C-language Source CodePéter Arató, Bence Csák. 727-736 [doi]