Abstract is missing.
- Context-aware resources placement for SRAM-based FPGA to minimize checkpoint/recovery overheadFouad Sahraoui, Ghaffari Fakhreddine, Mohamed El Amine Benkhelifa, Bertrand Granado. 1-6 [doi]
- Zero-latency datapath error correction framework for over-clocking DSP applications on FPGAsRui Policarpo Duarte, Christos-Savvas Bouganis. 1-7 [doi]
- An FPGA-based all-digital 802.11b & 802.15.4 receiver for the Software Defined Radio paradigmAlfredo Espinoza-Rhoton, Luis F. Gonzalez-Perez, J. L. Ponce, Borrayo-S. Hector, Lennin C. Yllescas Lennin, Ramon Parra-Michel, Hassan Aboushady. 1-6 [doi]
- Hardware/software infrastructure for ASIC commissioning and rapid system prototypingPeter Reichel, Jens Doge. 1-6 [doi]
- A high-level analysis of a multi-core vision processor using SystemC and TLM2.0Jones Yudi Mori, Michael Hübner. 1-6 [doi]
- Keynote - The past and future of FPGA soft processorsJan Gray. 1 [doi]
- A highly flexible reconfigurable system on a Xilinx FPGATomas Drahonovsky, Martin Rozkovec, Ondrej Novák. 1-6 [doi]
- On providing scalable self-healing adaptive fault-tolerance to RTR SoCsByron Navas, Johnny Öberg, Ingo Sander. 1-6 [doi]
- An AWF digital spectrometer for a radio telescopeHiroki Nakahara, Hiroyuki Nakanishi, Kazumasa Iwai. 1-6 [doi]
- LUT based secure cloud computing - An implementation using FPGAsLei Xu, Pham Dang Khoa, Seung-Hun Kim, Won Woo Ro, Weidong Shi. 1-6 [doi]
- A unified OpenCL-flavor programming model with scalable hybrid hardware platform on FPGAsHongyuan Ding, Miaoqing Huang. 1-7 [doi]
- FPGA-based design and implementation of direct torque control for induction machinesMohammad A. Zare, Rajesh G. Kavasseri, Cristinel Ababei. 1-6 [doi]
- Memory optimisation for hardware induction of axis-parallel decision treeChuan Cheng, Christos-Savvas Bouganis. 1-5 [doi]
- Enabling partial reconfiguration for coprocessors in mixed criticality multicore systems using PCI express single-root I/O virtualizationViet Vu Duy, Oliver Sander, Timo Sandmann, Steffen Bähr, Jan Heidelberger, Jürgen Becker. 1-6 [doi]
- High-throughput hash-based online traffic classification engines on FPGAVaibhav R. Gandhi, Yun R. Qu, Viktor K. Prasanna. 1-6 [doi]
- A power-efficient real-time architecture for SURF feature extractionC. Wilson, P. Zicari, S. Craciun, P. Gauvin, E. Carlisle, A. George, H. Lam. 1-8 [doi]
- Rotated parallel mapping: A novel approach for mapping data parallel applications on CGRAsSimon Schulz, Oliver Bringmann, Thomas Schweizer, Wolfgang Rosenstiel. 1-6 [doi]
- PAMS: Pattern Aware Memory System for embedded systemsTassadaq Hussain, Nehir Sönmez, Oscar Palomar, Osman S. Unsal, Adrián Cristal, Eduard Ayguadé, Mateo Valero, Shakaib A. Gursal. 1-7 [doi]
- What limits the operating frequency of a soft processor designKaveh Aasaraai, Andreas Moshovos. 1-6 [doi]
- Overloaded CDMA bus topology for MPSoC interconnectKhaled E. Ahmed, Mohammed M. Farag. 1-7 [doi]
- A practical scheme for implementing dynamic spectral precoding in OFDMEnrique Mariano Lizarraga, Graciela Corral-Briones. 1-6 [doi]
- Dynamic run-time hardware/software scheduling for 3D reconfigurable SoCQuang-Hai Khuat, Daniel Chillet, Michael Hubner. 1-4 [doi]
- High-performance FPGA implementations of volterra DFEs for optical fiber systemsAndreas Emeretlis, George Theodoridis, George-Othon Glentis. 1-8 [doi]
- A hardware architecture for filtering irreducible testorsVladimir Rodriguez, Jose F. Martinez, Jesús Ariel Carrasco-Ochoa, Manuel S. Lazo, René Cumplido, Claudia Feregrino Uribe. 1-4 [doi]
- Smart employment of circuit redundancy to effectively counter trojans (SECRET) in third-party IP coresMohammed M. Farag, Mohammad A. Ewais. 1-6 [doi]
- Side-channel power analysis of different protection schemes against fault attacks on AESPei Luo, Yunsi Fei, Liwei Zhang, A. Adam Ding. 1-6 [doi]
- 3D-LeukoNoC: A dynamic NoC protectionJohanna Sepúlveda, Guy Gogniat, Daniel Florez, Jean-Philippe Diguet, César Pedraza, Marius Strum. 1-6 [doi]
- Data path analysis for dynamic circuit specialisationTom Davidson, Dirk Stroobandt. 1-8 [doi]
- Stochastically computing discrete Fourier transform with reconfigurable digital fabricYu Bai, Mingjie Lin. 1-7 [doi]
- FPGA design and implementation of a matrix multiplier based accelerator for 3D EKF SLAMDaniel Tortei Tertei, Jonathan Piat, Michel Devy. 1-6 [doi]
- High-speed implementation of bcrypt password search using special-purpose hardwareFriedrich Wiemer, Ralf Zimmermann. 1-6 [doi]
- Efficient FPGA-based implementation of a CAZAC sequence generator for 3GPP LTEFelipe A. P. de Figueiredo, Fabiano S. Mathilde, Fabbryccio A. C. M. Cardoso, Rafael M. Vilela, Joao Paulo Miranda. 1-6 [doi]
- Energy-efficient histogram on FPGAAndrea Sanny, Yi-Hua E. Yang, Viktor K. Prasanna. 1-6 [doi]
- The FPGA implementation of an image registration algorithm using binary imagesAn Hung Nguyen, Mark R. Pickering, Andrew J. Lambert. 1-4 [doi]
- Dynamic protocol stacks in smart camera networksMarkus Happe, Yujiao Huang, Ariane Keller. 1-6 [doi]
- An architectural approach for reconfigurable industrial I/O devicesDaniel Kirschberger, Holger Flatt, Jürgen Jasperneite. 1-6 [doi]
- Phenox: Zynq 7000 based quadcopter robotRyo Konomura, Koichi Hori. 1-6 [doi]
- Keynote - SpaceCube - A family of reconfigurable hybrid on-board science data processorsThomas P. Flatley. 1-2 [doi]
- A generic pixel distribution architecture for parallel video processingKarim M. A. Ali, Rabie Ben Atitallah, Saïd Hanafi, Jean-Luc Dekeyser. 1-8 [doi]
- Enabling FPGA support in Matlab based heterogeneous systemsSam Skalicky, Tyler Kwolek, Sonia López, Marcin Lukowiak. 1-6 [doi]
- An AXI compatible cypress EZ-USB FX3 interface for USB-3.0 SuperSpeedBenedikt Jansen, Michael Hübner, Timo Jaeschke. 1-4 [doi]
- FPGA-based reconfigurable unit for real-time power quality index estimationMisael Lopez-Ramirez, Luis M. Ledesma-Carrillo, Ana L. Martinez-Herrera, Eduardo Cabal-Yepez, Homero Miranda-Vidales. 1-6 [doi]
- Tincr - A custom CAD tool framework for VivadoBrad White, Brent E. Nelson. 1-6 [doi]
- FPGA implementation of a reconfigurable image encryption systemM. T. Ramirez-Torres, J. S. Murguia, M. Mejia-Carlos. 1-4 [doi]
- TNT10G: A high-accuracy 10 GbE traffic player and recorder for multi-Terabyte tracesJose Fernando Zazo, Marco Forconesi, Sergio López-Buedo, Gustavo Sutter, Javier Aracil. 1-6 [doi]
- Characterization of OpenCL on a scalable FPGA architectureShanyuan Gao, Jeremy Chritz. 1-6 [doi]
- PoC-align: An open-source alignment accelerator using FPGAsThomas B. Preußer, Oliver Knodel, Rainer G. Spallek. 1-6 [doi]
- A hardware-assisted proof-of-concept for secure VoIP clients on untrusted operating systemsMaik Ender, Gerd Duppmann, Alexander Wild, Thomas Pöppelmann, Tim Guneysu. 1-6 [doi]
- Identifying homogenous reconfigurable regions in heterogeneous FPGAs for module relocationRico Backasch, Gerald Hempel, Stefan Werner, Sven Groppe, Thilo Pionteck. 1-6 [doi]
- Net reordering and multicommodity flow based global routing for FPGAsCristinel Ababei, Rajesh G. Kavasseri, Mohammad A. Zare. 1-6 [doi]
- Place Reservation technique for online task placement on a multi-context heterogeneous reconfigurable architectureQuang-Hoa Le, Emmanuel Casseau, Antoine Courtay. 1-6 [doi]
- Design of an attention detection system on the Zynq-7000 SoCFynn Schwiegelshohn, Michael Hübner. 1-6 [doi]
- Versatile educational and research robotic platform based on reconfigurable hardwareCarlos Andres Lara-Nino, Cesar Torres-Huitzil, Jose Hugo Barron-Zambrano. 1-6 [doi]
- On the performance and energy efficiency of FPGAs and GPUs for polyphase channelizationVignesh Adhinarayanan, Thaddeus Koehn, Krzysztof Kepa, Wu-chun Feng, Peter Athanas. 1-7 [doi]
- FPGA-based accelerator development for non-engineersDavid Uliana, Peter M. Athanas, Krzysztof Kepa. 1-6 [doi]
- A systematic study of lightweight hash functions on FPGAsBernhard Jungk, Leandro Rodrigues Lima, Matthias Hiller. 1-6 [doi]
- Area-efficient dynamically reconfigurable protocol-processing-hardware for access network communications SoCSaki Hatta, Nobuyuki Tanaka, Satoshi Shigematsu. 1-6 [doi]
- A framework for efficient rapid prototyping by virtually enlarging FPGA resourcesShinya Takamaeda-Yamazaki, Kenji Kise. 1-8 [doi]
- Embedding FPGA overlays into configurable Systems-on-Chip: ReconOS meets ZUMATobias Wiersema, Ame Bockhorn, Marco Platzner. 1-6 [doi]
- Force-directed scheduling for Data Flow Graph mapping on Coarse-Grained Reconfigurable ArchitecturesAlexander Fell, Zoltán Endre Rákossy, Anupam Chattopadhyay. 1-8 [doi]
- Mission control: A performance metric and analysis of control logic for pipelined architectures on FPGAsSam Skalicky, Sonia López, Marcin Lukowiak, Christopher Wood. 1-6 [doi]
- An adaptive victim cache schemeOsvaldo Navarro, Michael Hübner. 1-4 [doi]
- Fast and generic hardware architecture for stereo block matching applications on embedded systemsKonrad Häublein, Marc Reichenbach, Dietmar Fey. 1-6 [doi]
- Keynote - It's about timeEdward A. Lee. 1 [doi]
- Hardware Task-Status Manager for an RTOS with FIFO communicationPavel G. Zaykov, Georgi Kuzmanov, Anca Mariana Molnos, Kees G. W. Goossens. 1-8 [doi]
- 400 Gbps energy-efficient multi-field packet classification on FPGAShijie Zhou, Sihan Zhao, Viktor K. Prasanna. 1-6 [doi]
- Kernel-centric acceleration of high accuracy stereo-matchingTobias Kenter, Henning Schmitz, Christian Plessl. 1-8 [doi]
- Deferring accelerator offloading decisions to application runtimeGavin Vaz, Heinrich Riebler, Tobias Kenter, Christian Plessl. 1-8 [doi]
- A hardware generator for factor graph applicationsJames Demma, Peter Athanas. 1-8 [doi]
- FSM merging and reduction for IP cores watermarking using Genetic AlgorithmsJorge Echavarria, Alicia Morales-Reyes, René Cumplido, Miguel A. Salido. 1-7 [doi]
- Impact of defect tolerance techniques on the criticality of a SRAM-based mesh of cluster FPGAAdrien Blanchardon, Roselyne Chotin-Avot, Habib Mehrez, Emna Amouri. 1-6 [doi]
- The speed-up of detection of space debris using "InterP" and "FLOPS2D"Naoyuki Fujita, Toshifumi Yanagisawa, Hirohisa Kurosaki, Hiroshi Oda. 1-6 [doi]
- Power analysis attack on hardware implementation of MAC-Keccak on FPGAsPei Luo, Yunsi Fei, Xin Fang, A. Adam Ding, Miriam Leeser, David R. Kaeli. 1-7 [doi]
- Advanced branch predictors for soft processorsDi Wu, Andreas Moshovos. 1-6 [doi]
- RAR-NoC: A reconfigurable and adaptive routable Network-on-Chip for FPGA-based multiprocessor systemsJens Rettkowski, Diana Göhringer. 1-6 [doi]
- An a-FPGA architecture for relative timing based asynchronous designsJotham Vaddaboina Manoranjan, Kenneth S. Stevens. 1-6 [doi]
- Adaptive and reconfigurable fault-tolerant routing method for 2D Networks-on-ChipPoona Bahrebar, Dirk Stroobandt. 1-8 [doi]
- Can high-level synthesis compete against a hand-written code in the cryptographic domain? A case studyEkawat Homsirikamol, Kris Gaj. 1-8 [doi]
- A device-agnostic tool for precomputing legal placements in modular design flowsAli Asgar Sohanghpurwala, Peter M. Athanas, Andrew Love. 1-5 [doi]
- Spiking dynamic neural fields architectures on FPGABenoit Chappet de Vangel, Cesar Torres-Huitzil, Bernard Girau. 1-6 [doi]
- A conceptual toolchain for an application domain specific reconfigurable logic architectureTimm Bostelmann, Sergei Sawitzki. 1-4 [doi]
- Low power RAM-based hierarchical CAM on FPGAZhuo Qian, Martin Margala. 1-4 [doi]
- Parameterised FPGA reconfigurations for efficient test set generationAlexandra Kourfali, Elias Vansteenkiste, Dirk Stroobandt. 1-6 [doi]
- Improving reconfiguration speed for dynamic circuit specialization using placement constraintsAmit Kulkarni, Tom Davidson, Karel Heyse, Dirk Stroobandt. 1-6 [doi]
- Automatic cache partitioning and time-triggered scheduling for real-time MPSoCsGang Chen, Biao Hu, Kai Huang 0001, Alois Knoll, Kai Huang, Di Liu, Todor Stefanov. 1-8 [doi]