B. P. Harish - researchr alias

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Viewing Publication 1 - 12 from 12

2022

A Novel Feasibility Test for Energy Minimization of Real-Time Mixed Task Sets for DVS-Enabled Uniprocessor SystemH. T. Manohara, B. P. Harish. jcsc, 31(3), 2022. [doi]

2020

Process-induced variability modeling of subthreshold leakage power considering device stackingAnala M. Reddy, B. P. Harish. ijhcitp, 48(5):739-749, 2020. [doi]

Process-induced variability modeling of subthreshold leakage power considering device stackingAnala M. Reddy, B. P. Harish. ijcta, 48(5):739-749, 2020. [doi]

Artificial Neural Network Model for Design Optimization of 2-stage Op-ampHarsha M. V., B. P. Harish. vdat 2020: 1-5 [doi]

2019

Process Variation-Aware Analytical Modeling of Subthreshold Leakage PowerAnala M., B. P. Harish. patmos 2019: 119-124 [doi]

Dynamic Supply Voltage Level Generation for Minimum Energy Real Time Tasks using Geometric ProgrammingH. T. Manohara, B. P. Harish. socc 2019: 376-381 [doi]

2018

Analytical Modeling of Process Variability in Subthreshold Regime for Ultra Low Power ApplicationsAnala M., B. P. Harish. apccas 2018: 257-260 [doi]

An Integrated MaxFit Genetic Algorithm-SPICE Framework for 2-Stage Op-Amp Design AutomationHarsha M. V., B. P. Harish. isvlsi 2018: 170-174 [doi]

2009

Bridging Technology-CAD and Design-CAD for Variability Aware Nano-CMOS CircuitsB. P. Harish, Navakanta Bhat, Mahesh B. Patil. iscas 2009: 2309-2312 [doi]

2008

Hybrid-CV Modeling for Estimating the Variability in Dynamic PowerB. P. Harish, Navakanta Bhat, Mahesh B. Patil. jolpe, 4(3):263-274, 2008. [doi]

2007

Process Variability-Aware Statistical Hybrid Modeling of Dynamic Power Dissipation in 65 nm CMOS DesignsB. P. Harish, Navakanta Bhat, Mahesh B. Patil. iccta 2007: 94-98 [doi]

On a Generalized Framework for Modeling the Effects of Process Variations on Circuit Delay Performance Using Response Surface MethodologyB. P. Harish, Navakanta Bhat, Mahesh B. Patil. tcad, 26(3):606-614, 2007. [doi]

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