Donald L. Dietmeyer - researchr alias

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Viewing Publication 1 - 25 from 25

1998

Exploiting near symmetry in multilevel logic synthesisFeng Wang, Donald L. Dietmeyer. tcad, 17(9):772-781, 1998. [doi]

1993

Generating minimal covers of symmetric functionsDonald L. Dietmeyer. tcad, 12(5):710-713, 1993. [doi]

1992

Three Decades of HDLs: Part I, CDL Through TI-HDLYaohan Chu, Donald L. Dietmeyer, James R. Duley, Fredrick J. Hill, Mario Barbacci, Charles W. Rose, Greg Ordy, Bill Johnson, Martin Roberts. dt, 9(2):69-81, 1992. [doi]

Multilevel logic synthesis with extended arraysBo-Gwan Kim, Donald L. Dietmeyer. tcad, 11(2):142-157, 1992. [doi]

1991

Multilevel logic synthesis of symmetric switching functionsBo-Gwan Kim, Donald L. Dietmeyer. tcad, 10(4):436-446, 1991. [doi]

1987

Local Transformations via Cube OperationsDonald L. Dietmeyer. tcad, 6(5):892-902, 1987. [doi]

1983

CONLAN ReportRobert Piloty, Dominique Borrione, Mario Barbacci, Donald L. Dietmeyer, Fredrick J. Hill, Patrick Skelly. Volume 151 of Lecture Notes in Computer Science, Springer, 1983.

1980

CONLAN: a formal construction method for hardware description languages: basic principlesRobert Piloty, Mario Barbacci, Dominique Borrione, Donald L. Dietmeyer, Fredrick J. Hill, Patrick Skelly. afips 1980: 209-217 [doi]

CONLAN: a formal construction method for hardware description languages: language applicationRobert Piloty, Mario Barbacci, Dominique Borrione, Donald L. Dietmeyer, Fredrick J. Hill, Patrick Skelly. afips 1980: 229-236 [doi]

CONLAN: a formal construction method for hardware description languages: language derivationRobert Piloty, Mario Barbacci, Dominique Borrione, Donald L. Dietmeyer, Fredrick J. Hill, Patrick Skelly. afips 1980: 219-227 [doi]

An Overview of CONLAN: A Formal Construction Method for Hardware Description LanguageRobert Piloty, Mario Barbacci, Dominique Borrione, Donald L. Dietmeyer, Fredrick J. Hill, Patrick Skelly. ifip 1980: 199-204

1974

Introducing DDLDonald L. Dietmeyer. Computer, 7(12):34-38, 1974. [doi]

1973

Fast State Minimization of Incompletely Specified Sequential MachinesParveen K. Gupta, Donald L. Dietmeyer. TC, 22(2):215-217, 1973. [doi]

1971

The Avoidance and Elimination of Function Hazards in Asynchronous Sequential CircuitsRolland R. Hackbart, Donald L. Dietmeyer. TC, 20(2):184-189, 1971. [doi]

1969

Logic Design Automation of Fan-In Limited NAND NetworksDonald L. Dietmeyer, Yueh-Hsung Su. TC, 18(1):11-22, 1969. [doi]

Translation of a DDL Digital System Specification to Boolean EquationsJames R. Duley, Donald L. Dietmeyer. TC, 18(4):305-313, 1969. [doi]

Computer Reduction of Two-Level, Multiple-Output Switching CircuitsYueh-Hsung Su, Donald L. Dietmeyer. TC, 18(1):58-63, 1969. [doi]

1968

Generating prime implicants via ternary encoding and decimal arithmeticDonald L. Dietmeyer. CACM, 11(7):520-523, 1968. [doi]

Bounds on the Period of Oscillatory Activity in Randomly Interconnected Networks of Neuron-Like ElementsDonald L. Dietmeyer. TC, 17(6):578-591, 1968. [doi]

A Digital System Design Language (DDL)James R. Duley, Donald L. Dietmeyer. TC, 17(9):850-861, 1968. [doi]

An Algorithm for Synthesis of Multiple-Output Combinational LogicPeter R. Schneider, Donald L. Dietmeyer. TC, 17(2):117-128, 1968. [doi]

1967

Identification of Symmetry, Redundancy and Equivalence of Boolean FunctionsDonald L. Dietmeyer, Peter R. Schneider. TC, 16(6):804-817, 1967. [doi]

1965

A Computer-Oriented Factoring Algorithm for NOR Logic DesignDonald L. Dietmeyer, Peter R. Schneider. TC, 14(6):868-874, 1965. [doi]

1963

A Magnetic Ternary DeviceD. J. Anderson, Donald L. Dietmeyer. TC, 12(6):911-914, 1963. [doi]

Conversion from Positive to Negative and Imaginary RadixDonald L. Dietmeyer. TC, 12(1):20-22, 1963. [doi]

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