J. Urresti - researchr alias

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Viewing Publication 1 - 5 from 5

2014

3.3 kV PT-IGBT with voltage-sensor monolithically integratedJ. Urresti, Salvador Hidalgo, D. Flores, D. Ferna'ndez Hevia. iet-cds, 8(3):182-187, 2014. [doi]

2012

Study of layout influence on ruggedness of NPT-IGBT devices by physical modellingI. Cortés, X. Perpiñà, J. Urresti, Xavier Jordà, J. Rebollo. mr, 52(9-10):2471-2476, 2012. [doi]

2005

Analysis of hot-carrier degradation in a SOI LDMOS transistor with a steep retrograde drift doping profileI. Cortés, J. Roig, D. Flores, J. Urresti, S. Hidalgo, J. Rebollo. mr, 45(3-4):493-498, 2005. [doi]

Lateral punch-through TVS devices for on-chip protection in low-voltage applicationsJ. Urresti, S. Hidalgo, D. Flores, J. Roig, I. Cortés, J. Rebollo. mr, 45(7-8):1181-1186, 2005. [doi]

2003

Optimisation of very low voltage TVS protection devicesJ. Urresti, S. Hidalgo, D. Flores, J. Roig, J. Rebollo, I. Mazarredo. mj, 34(9):809-813, 2003. [doi]

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