James H. Mulligan Jr. - researchr alias

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Viewing Publication 1 - 10 from 10

1997

Incorporating interconnect, register, and clock distribution delays into the retiming processTolga Soyata, Eby G. Friedman, James H. Mulligan Jr.. tcad, 16(1):105-120, 1997. [doi]

1995

Monotonicity Constraints on Path Delays for Efficient Retiming with Localized Clock Skew and Variable Register DelayTolga Soyata, Eby G. Friedman, James H. Mulligan Jr.. iscas 1995: 1748-1751

1994

Optimization of phase-locked loop performance in data recovery systemsRamon S. Co, James H. Mulligan Jr.. jssc, 29(9):1022-1034, September 1994. [doi]

1993

Integration of Clock Skew and Register Delays into a Retiming AlgorithmTolga Soyata, Eby G. Friedman, James H. Mulligan Jr.. iscas 1993: 1483-1486

Multiple training concept for back-propagation neural networks for use in associative memoriesYeou-Fang Wang, Jose B. Cruz Jr., James H. Mulligan Jr.. NN, 6(8):1169-1175, 1993. [doi]

1991

Clock frequency and latency in synchronous digital systemsEby G. Friedman, James H. Mulligan Jr.. tsp, 39(4):930-934, 1991. [doi]

Guaranteed recall of all training pairs for bidirectional associative memoryYeou-Fang Wang, Jose B. Cruz Jr., James H. Mulligan Jr.. tnn, 2(6):559-567, 1991. [doi]

1990

Two coding strategies for bidirectional associative memoryYeou-Fang Wang, Jose B. Cruz Jr., James H. Mulligan Jr.. tnn, 1(1):81-92, 1990. [doi]

On multiple training for bidirectional associative memoryYeou-Fang Wang, Jose B. Cruz Jr., James H. Mulligan Jr.. tnn, 1(3):275-276, 1990. [doi]

1959

A Figure of Merit for Single-Pass Data Recording SystemsJames H. Mulligan Jr.. TC, 8(1):48-54, 1959. [doi]

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