Lounis Kessal - researchr alias

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Viewing Publication 1 - 23 from 23

2023

Implementation of a Bio-Inspired Neural Architecture for Autonomous Vehicles on a Multi-FPGA PlatformTarek Elouaret, Sylvain Colomer, Frédéric de Melo, Nicolas Cuperlier, Olivier Romain, Lounis Kessal, Stéphane Zuckerman. sensors, 23(10):4631, 2023. [doi]

2022

Implementation of a bio-inspired neural architecture for autonomous vehicle on a reconfigurable platformTarek Elouaret, Sylvain Colomer, Frederic de Melo, Nicolas Cuperlier, Olivier Romain, Lounis Kessal, Stéphane Zuckerman. visalg 2022: 661-666 [doi]

2019

2018

Lightweight Hardware Architecture for Probabilistic Gradient Descent Bit Flipping on QC-LDPC CodesKhoa Le, Fakhreddine Ghaffari, Lounis Kessal, David Declercq, Valentin Savin, Oana Boncalo. iscas 2018: 1-5 [doi]

Variable-Node-Shift Based Architecture for Probabilistic Gradient Descent Bit Flipping on QC-LDPC CodesKhoa LeTrung, David Declercq, Fakhreddine Ghaffari, Lounis Kessal, Oana Boncalo, Valentin Savin. tcas, 65-I(7):2183-2195, 2018. [doi]

2014

FPGA-implementation of a bio-inspired medical hearing aid based DWT-OLALotfi Bendaouia, Hassen Salhi, Si Mahmoud Karabernou, Lounis Kessal, Fayçal Ykhlef. icalip 2014: 806-811 [doi]

2012

Enhancing Reconfigurable Platforms Programmability for Synchronous Data-Flow ApplicationsLaurent Gantel, Amel Khiar, Benoit Miramond, Mohamed El Amine Benkhelifa, Lounis Kessal, Fabrice Lemonnier, Jimmy Le Rhun. trets, 5(3):14, 2012. [doi]

2011

Dataflow programming model for reconfigurable computingLaurent Gantel, Amel Khiar, Benoit Miramond, Mohamed El Amine Benkhelifa, Fabrice Lemonnier, Lounis Kessal. recosoc 2011: 1-8 [doi]

2009

Hardware Architecture for Pattern Recognition in Gamma-Ray ExperimentSonia Khatchadourian, Jean-Christophe Prévotet, Lounis Kessal. ejes, 2009, 2009. [doi]

2008

Reconfigurable computing: design methodology and hardware tasks scheduling for real-time image processingLounis Kessal, Nicolas Abel, Si Mahmoud Karabernou, Didier Demigny. jrtip, 3(3):131-147, 2008. [doi]

Neural network hardware architecture for pattern recognition in the HESS2 projectNarayanan Ramanan, Sonia Khatchadourian, Jean-Christophe Prévotet, Lounis Kessal. esann 2008: 343-348 [doi]

2007

Erratum to Real-time FPGA implementation of Hough Transform using gradient and CORDIC algorithm [Image and Vision Computing 23 (2005) 1009-1017]Si Mahmoud Karabernou, Lounis Kessal, Fayçal Terranti. ivc, 25(6):1032, 2007. [doi]

2006

Clear Stream towards Dynamically Reconfigurable Systems on ChipNicolas Abel, Lounis Kessal, Sébastien Pillement, Didier Demigny. recosoc 2006: 98-104

2004

Design flexibility using fpga dynamical reconfigurationNicolas Abel, Lounis Kessal, Didier Demigny. icip 2004: 2821-2824

2003

Real-time image processing with dynamically reconfigurable architectureLounis Kessal, Nicolas Abel, Didier Demigny. rti, 9(5):297-313, 2003. [doi]

2001

Fast Recursive Implementation of the Gaussian FilterDidier Demigny, Lounis Kessal, J. Pons. ifip10-5 2002: 39-49

Reconfigurable Architecture Using High Speed FPGALounis Kessal, R. Bourguiba, Didier Demigny, N. Boudouani, M. Karabernou. ifip10-5 2002: 75-86

Two ASIC for Low and Middle Levels of Real Time Image ProcessingP. Lamaty, B. Mazar, Didier Demigny, Lounis Kessal, M. Karabernou. ifip10-5 2002: 3-14

2000

How to Use High Speed Reconfigurable FPGA for Real Time Image Processing?Didier Demigny, Lounis Kessal, R. Bourguiba, N. Boudouani. camp 2000: 240 [doi]

Reconfigurable Hardware for Real Time Image ProcessingLounis Kessal, Didier Demigny, N. Boudouani, R. Bourgiba. icip 2000: 110-113

1997

Efficient ASIC and FPGA Implementations of IIR Filters for Real Time Edge DetectionF. G. Lorca, Lounis Kessal, Didier Demigny. icip 1997: 406-409 [doi]

1995

Evaluation of edge detectors performances with a discrete expression of Canny s criteriaDidier Demigny, F. G. Lorca, Lounis Kessal. icip 1995: 2169-2172 [doi]

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