Michael Ogbonna Esonu - researchr alias

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Viewing Publication 1 - 8 from 8

1995

Design techniques for fault-tolerant systolic arraysMichael Ogbonna Esonu, Asim J. Al-Khalili, Salim Hariri, Dhamin Al-Khalili. vlsisp, 11(1-2):151-168, 1995. [doi]

Area efficient computing structures for concurrent error detection in systolic arraysMichael Ogbonna Esonu, Asim J. Al-Khalili, Salim Hariri. vlsisp, 10(3):237-260, 1995. [doi]

1994

Fault Characterization and Testability Analysis of Emitter Coupled Logic and Comparison with CMOS & BiCMOS CircuitsMichael Ogbonna Esonu, Dhamin Al-Khalili, Côme Rozon. vlsi, 1(4):261-276, 1994. [doi]

1993

Fault Characterization and Testability Analysis of Emitter Coupled Logic and Comparison with CMOS & BiCMOS CircuitsMichael Ogbonna Esonu, Dhamin Al-Khalili, Come Rozon. iscas 1993: 1714-1717

1992

Design Methodology for Fault-Tolerant Systolic Array ArchitecturesMichael Ogbonna Esonu, Asim J. Al-Khalili, Salim Hariri. icpp 1992: 267-274

1991

Area Efficient Computing Structures for Concurrent Error Detection in Systolic ArchitecturesMichael Ogbonna Esonu, Asim J. Al-Khalili, Salim Hariri. icpp 1991: 484-491

On the Design of Optimal Fault-Tolerant Systolic Array ArchitecuresMichael Ogbonna Esonu, Asim J. Al-Khalili, Salim Hariri. ipps 1991: 352-357

1990

Design of optimal systolic arrays: a systematic approachMichael Ogbonna Esonu, Asim J. Al-Khalili, Salim Hariri. spdp 1990: 166-173 [doi]

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