Narendra Vallepalli - researchr alias

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Viewing Publication 1 - 2 from 2

2006

A 3-GHz 70-mb SRAM in 65-nm CMOS technology with integrated column-based dynamic power supplyKevin Zhang, Uddalak Bhattacharya, Zhanping Chen, Fatih Hamzaoglu, Daniel Murray, Narendra Vallepalli, Yih Wang, Bo Zheng, Mark Bohr. jssc, 41(1):146-151, 2006. [doi]

2005

SRAM design on 65-nm CMOS technology with dynamic sleep transistor for leakage reductionKevin Zhang, Uddalak Bhattacharya, Zhanping Chen, Fatih Hamzaoglu, Daniel Murray, Narendra Vallepalli, Yih Wang, Bo Zheng, Mark Bohr. jssc, 40(4):895-901, 2005. [doi]

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