Paul Tschirhart - researchr alias

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Viewing Publication 1 - 6 from 6

2016

Fast full system memory checkpointing with SSD-aware memory controllerJim Stevens, Paul Tschirhart, Bruce Jacob. memsys 2016: 96-98 [doi]

The Case for Associative DRAM CachesPaul Tschirhart, Jim Stevens, Zeshan Chishti, Bruce Jacob. memsys 2016: 211-219 [doi]

2015

The Semantic Gap Between Software and the Memory SystemJim Stevens, Paul Tschirhart, Bruce Jacob. memsys 2015: 43-46 [doi]

Multi-Level Main Memory Systems: Technology Choices, Design Considerations, and Trade-off AnalysisPaul Tschirhart. PhD thesis, University of Maryland, College Park, MD, USA, 2015. [doi]

Bringing Modern Hierarchical Memory Systems Into Focus: A study of architecture and workload factors on system performancePaul Tschirhart, Jim Stevens, Zeshan Chishti, Shih-Lien Lu, Bruce Jacob. memsys 2015: 179-190 [doi]

2014

Using participation factors to improve the consistency and accuracy of Prony analysis for voltage stability monitoring applicationsPaul Tschirhart, Alan Sussman, Eyad H. Abed. isgt 2014: 1-5 [doi]

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