Table of Contents

• Large-Memory Nodes for Energy Efficient High-Performance ComputingDarko Zivanovic, Milan Radulovic, Germán Llort, David Zaragoza, Janko Strassburg, Paul M. Carpenter, Petar Radojkovic, Eduard Ayguadé. 3-9 [doi]
• A New Metric to Measure Cache Utilization for HPC WorkloadsAditya M. Deshpande, Jeffrey T. Draper. 10-17 [doi]
• Checkpointing Exascale Memory Systems with Existing Memory TechnologiesNilmini Abeyratne, Hsing-Min Chen, Byoungchan Oh, Ronald G. Dreslinski, Chaitali Chakrabarti, Trevor N. Mudge. 18-29 [doi]
• Exposing the Locality of Heterogeneous Memory Architectures to HPC ApplicationsBrice Goglin. 30-39 [doi]
• Performance Impact of a Slower Main Memory: A case study of STT-MRAM in HPCKazi Asifuzzaman, Milan Pavlovic, Milan Radulovic, David Zaragoza, Ohseong Kwon, Kyung-Chang Ryoo, Petar Radojkovic. 40-49 [doi]
• Nswap2L: Transparently Managing Heterogeneous Cluster Storage Resources for Fast SwappingTia Newhall, E. Ryerson Lehman-Borer, Benjamin Marks. 50-61 [doi]
• Low Latency, High Bisection-Bandwidth Networks for Exascale Memory SystemsShang Li, Po-Chun Huang, David Banks, Max DePalma, Ahmed Elshaarany, Scott Hemmert, Arun Rodrigues, Emily Ruppel, Yitian Wang, Jim Ang, Bruce Jacob. 62-73 [doi]
• Write Locality and Optimization for Persistent MemoryDong Chen, Chencheng Ye, Chen Ding. 77-87 [doi]
• Multi-Level Memory Policies: What You Add Is More Important Than What You Take OutSimon D. Hammond, Arun F. Rodrigues, Gwendolyn R. Voskuilen. 88-93 [doi]
• DRAMPersist: Making DRAM Systems PersistentKrishna T. Malladi, Manu Awasthi, Hongzhong Zheng. 94-95 [doi]
• Fast full system memory checkpointing with SSD-aware memory controllerJim Stevens, Paul Tschirhart, Bruce Jacob. 96-98 [doi]
• Challenges of Programming a System with Heterogeneous Memories and Heterogeneous Processors: A Programmer's ViewShuai Che, Arkaprava Basu, Jonathan Gallmeier. 99-103 [doi]
• Analytical Study on Bandwidth Efficiency of Heterogeneous Memory SystemsAmin Farmahini Farahani, David Roberts, Nuwan Jayasena. 104-118 [doi]
• Adaptive Row Addressing for Cost-Efficient Parallel Memory Protocols in Large-Capacity MemoriesDmitry Knyaginin, Vassilis Papaefstathiou, Per Stenström. 121-132 [doi]
• Co-DIMM: Inter-Socket Data Sharing via a Common DIMM ChannelKe Zhang, Lei Yu, Yisong Chang, Ran Zhao, Hongxia Zhang, Lixin Zhang, Mingyu Chen, Sally A. McKee. 133-141 [doi]
• Exploring Time and Energy for Complex Accesses to a Hybrid Memory CubeJuri Schmidt, Holger Fröning, Ulrich Brüning. 142-150 [doi]
• Analyzing Consistency Issues in HMC AtomicsPranith Kumar, Lifeng Nai, Hyesoon Kim. 151-152 [doi]
• Exploring Tag-Bit Memory Operations in Hybrid Memory CubesJohn D. Leidel, Yong Chen. 153-163 [doi]
• Twin-Load: Bridging the Gap between Conventional Direct-Attached and Buffer-on-Board Memory SystemsZehan Cui, Tianyue Lu, Sally A. McKee, Mingyu Chen, Haiyang Pan, Yuan Ruan. 164-176 [doi]
• Concurrent Dynamic Memory Coalescing on GoblinCore-64 ArchitectureXi Wang, John D. Leidel, Yong Chen. 177-187 [doi]
• Dense Footprint Cache: Capacity-Efficient Die-Stacked DRAM Last Level CacheSeunghee Shin, Sihong Kim, Yan Solihin. 191-203 [doi]
• Analyzing allocation behavior for multi-level memoryGwendolyn Voskuilen, Arun F. Rodrigues, Simon D. Hammond. 204-207 [doi]
• Processing Acceleration with Resistive Memory-based ComputationMohsen Imani, Yan Cheng, Tajana Rosing. 208-210 [doi]
• The Case for Associative DRAM CachesPaul Tschirhart, Jim Stevens, Zeshan Chishti, Bruce Jacob. 211-219 [doi]
• Prefetching as a Potentially Effective Technique for Hybrid Memory OptimizationMahzabeen Islam, Soumik Banerjee, Mitesh Meswani, Krishna M. Kavi. 220-231 [doi]
• Replacement Policies for Heterogeneous MemoriesJacob Brock, Chencheng Ye, Chen Ding. 232-237 [doi]
• How Many MLCs Should Impersonate SLCs to Optimize SSD Performance?Wei Wang, Wen Pan, Tao Xie, Deng Zhou. 238-247 [doi]
• Languages Must Expose Memory HeterogeneityXiaochen Guo, Aviral Shrivastava, Michael Spear, Gang Tan. 251-256 [doi]
• ConGen: An Application Specific DRAM Memory Controller GeneratorMatthias Jung 0001, Deepak M. Mathew, Christian Weis, Norbert Wehn, Irene Heinrich, Marco V. Natale, Sven O. Krumke. 257-267 [doi]
• Applying Software-based Memory Error Correction for In-Memory Key-Value Store: Case Studies on Memcached and RAMCloudYin Li, Hao Wang, Xiaoqing Zhao, Hongbin Sun, Tong Zhang. 268-278 [doi]
• Software Assisted Hardware Cache Coherence for Heterogeneous ProcessorsArkaprava Basu, Sooraj Puthoor, Shuai Che, Bradford M. Beckmann. 279-288 [doi]
• Improving DRAM Bandwidth Utilization with MLP-Aware OS PagingRishiraj A. Bheda, Thomas M. Conte, Jeffrey S. Vetter. 289-294 [doi]
• Data-Centric Computing Frontiers: A Survey On Processing-In-MemoryPatrick Siegl, Rainer Buchty, Mladen Berekovic. 295-308 [doi]
• HAPPY: Hybrid Address-based Page Policy in DRAMsMohsen Ghasempour, Aamer Jaleel, Jim D. Garside, Mikel Luján. 311-321 [doi]
• AWARD: Approximation-aWAre Restore in Further Scaling DRAMXianWei Zhang, Youtao Zhang, Bruce R. Childers, Jun Yang. 322-324 [doi]
• DRAMScale: Mechanisms to Increase DRAM CapacityKrishna T. Malladi, Uksong Kang, Manu Awasthi, Hongzhong Zheng. 325-326 [doi]
• On the Use of DRAM with Unrepaired Weak Cells in Computing SystemsHao Wang, Yin Li, Xuebin Zhang, Xiaoqing Zhao, Hongbin Sun, Tong Zhang. 327-337 [doi]
• CLARA: Circular Linked-List Auto and Self Refresh ArchitectureAditya Agrawal, Mike O'Connor, Evgeny Bolotin, Niladrish Chatterjee, Joel S. Emer, Stephen W. Keckler. 338-349 [doi]
• MicroRefresh: Minimizing Refresh Overhead in DRAM CachesNagendra Gulur, R. Govindarajan, Mahesh Mehendale. 350-361 [doi]
• DReAM: Dynamic Re-arrangement of Address Mapping to Improve the Performance of DRAMsMohsen Ghasempour, Aamer Jaleel, Jim D. Garside, Mikel Luján. 362-373 [doi]
• Photonic Interconnects for Interposer-based 2.5D/3D Integrated Systems on a ChipPaolo Grani, Roberto Proietti, Venkatesh Akella, S. J. Ben Yoo. 377-386 [doi]
• Understanding the Impact of Air and Microfluidics Cooling on Performance of 3D Stacked Memory SystemsSyed Minhaj Hassan, Sudhakar Yalamanchili. 387-394 [doi]
• Reliability and Performance Trade-off Study of Heterogeneous MemoriesManish Gupta, David Roberts, Mitesh Meswani, Vilas Sridharan, Dean M. Tullsen, Rajesh K. Gupta. 395-401 [doi]
• Integrated Thermal Analysis for Processing In Die-Stacking MemoryYuxiong Zhu, Borui Wang, Dong Li, Jishen Zhao. 402-414 [doi]
• TAPAS: Temperature-aware Adaptive Placement for 3D Stacked Hybrid CachesMajed Valad Beigi, Gokhan Memik. 415-426 [doi]
• Characterizing the Performance of Hybrid Memory Cube Using ApexMAP Application ProbesKhaled Z. Ibrahim, Farzad Fatollahi-Fard, David Donofrio, John Shalf. 429-436 [doi]
• Evaluating the feasibility of storage class memory as main memoryG. Scott Lloyd, Maya Gokhale. 437-441 [doi]
• Using Memristor Technology for Multi-value Registers in Signed-digit Arithmetic CircuitsDietmar Fey, Marc Reichenbach, Christopher Söll, Mehrdad Biglari, Jürgen Röber, Robert Weigel. 442-454 [doi]
• A Validation of DRAM RAPL Power MeasurementsSpencer Desrochers, Chad Paradis, Vincent M. Weaver. 455-470 [doi]
• Reverse Engineering of DRAMs: Row Hammer with CrosshairMatthias Jung 0001, Carl Christian Rheinländer, Christian Weis, Norbert Wehn. 471-476 [doi]