Abstract is missing.
- Interconnect-Memory Challenges for Multi-chip, Silicon Interposer SystemsGabriel H. Loh, Natalie D. Enright Jerger, Ajaykumar Kannan, Yasuko Eckert. 3-10 [doi]
- Near Data Processing: Impact and Optimization of 3D Memory System Architecture on the UncoreSyed Minhaj Hassan, Sudhakar Yalamanchili, Saibal Mukhopadhyay. 11-21 [doi]
- Opportunities and Challenges of Performing Vector Operations inside the DRAMMarco Antonio Zanata Alves, Paulo C. Santos, Matthias Diener, Luigi Carro. 22-28 [doi]
- SIMT-based Logic Layers for Stacked DRAM Architectures: A PrototypeChad D. Kersey, Sudhakar Yalamanchili, Hyesoon Kim. 29-30 [doi]
- Another Trip to the Wall: How Much Will Stacked DRAM Benefit HPC?Milan Radulovic, Darko Zivanovic, Daniel Ruiz, Bronis R. de Supinski, Sally A. McKee, Petar Radojkovic, Eduard Ayguadé. 31-36 [doi]
- A Data Centric Perspective on Memory PlacementYitzhak Birk, Oskar Mencer. 39-42 [doi]
- The Semantic Gap Between Software and the Memory SystemJim Stevens, Paul Tschirhart, Bruce Jacob. 43-46 [doi]
- MMC: a Many-core Memory Connection ModelChen Ding, Hao Lu, Chencheng Ye. 47-50 [doi]
- High Performance Computing Co-Design StrategiesJames A. Ang. 51-52 [doi]
- Opportunities to Upgrade Main MemoryDave Resnick. 55-59 [doi]
- E-ECC: Low Power Erasure and Error Correction Schemes for Increasing Reliability of Commodity DRAM SystemsHsing-Min Chen, Akhil Arunkumar, Carole-Jean Wu, Trevor N. Mudge, Chaitali Chakrabarti. 60-70 [doi]
- Writing without Disturb on Phase Change Memories by Integrating Coding and Layout DesignAli Eslami, Alfredo Velasco, Alireza Vahid, Georgios Mappouras, A. Robert Calderbank, Daniel J. Sorin. 71-77 [doi]
- Achieving Yield, Density and Performance Effective DRAM at Extreme Technology SizesBruce R. Childers, Jun Yang, Youtao Zhang. 78-84 [doi]
- Omitting Refresh: A Case Study for Commodity and Wide I/O DRAMsMatthias Jung 0001, Éder Zulian, Deepak M. Mathew, Matthias Herrmann, Christian Brugger, Christian Weis, Norbert Wehn. 85-91 [doi]
- Implications of Memory Interference for Composed HPC ApplicationsBrian Kocoloski, Yuyu Zhou, Bruce R. Childers, John Lange. 95-97 [doi]
- Software Techniques for Scratchpad Memory ManagementPaul Sebexen, Thomas Sohmers. 98-102 [doi]
- Dynamic Memory Pressure Aware BallooningJinchun Kim, Viacheslav V. Fedorov, Paul V. Gratz, A. L. Narasimha Reddy. 103-112 [doi]
- Shared Last-Level Caches and The Case for Longer TimeslicesViacheslav V. Fedorov, A. L. Narasimha Reddy, Paul V. Gratz. 113-120 [doi]
- S-L1: A Software-based GPU L1 Cache that Outperforms the Hardware L1 for Data Processing ApplicationsReza Mokhtari, Michael Stumm. 121-132 [doi]
- Architecture Exploration for Data Intensive ApplicationsFernando Martin del Campo, Paul Chow. 135-145 [doi]
- MEMST: Cloning Memory Behavior using Stochastic TracesGanesh Balakrishnan, Yan Solihin. 146-157 [doi]
- Modeling Data Movement in the Memory Hierarchy in HPC SystemsAditya M. Deshpande, Jeffrey T. Draper. 158-161 [doi]
- Rethinking Design Metrics for Datacenter DRAMManu Awasthi. 162-163 [doi]
- HpMC: An Energy-aware Management System of Multi-level Memory ArchitecturesChun-Yi Su, David Roberts, Edgar A. León, Kirk W. Cameron, Bronis R. de Supinski, Gabriel H. Loh, Dimitrios S. Nikolopoulos. 167-178 [doi]
- Bringing Modern Hierarchical Memory Systems Into Focus: A study of architecture and workload factors on system performancePaul Tschirhart, Jim Stevens, Zeshan Chishti, Shih-Lien Lu, Bruce Jacob. 179-190 [doi]
- The Potential and Perils of Multi-Level MemoryJagan Jayaraj, Arun F. Rodrigues, Simon D. Hammond, Gwendolyn R. Voskuilen. 191-196 [doi]
- k-Means Clustering on Two-Level Memory SystemsMichael A. Bender, Jonathan W. Berry, Simon D. Hammond, Branden Moore, Benjamin Moseley, Cynthia A. Phillips. 197-205 [doi]
- Towards Workload-Aware Page Cache Replacement Policies for Hybrid MemoriesAhsen J. Uppal, Mitesh R. Meswani. 206-219 [doi]
- Anatomy of GPU Memory System for Multi-Application ExecutionAdwait Jog, Onur Kayiran, Tuba Kesten, Ashutosh Pattnaik, Evgeny Bolotin, Niladrish Chatterjee, Stephen W. Keckler, Mahmut T. Kandemir, Chita R. Das. 223-234 [doi]
- Inefficiencies in the Cache Hierarchy: A Sensitivity Study of Cacheline Size with Mobile WorkloadsAnouk Van Laer, William Wang, Christopher D. Emmons. 235-245 [doi]
- Herniated Hash Tables: Exploiting Multi-Level Phase Change Memory for In-Place Data ExpansionZhaoxia Deng, Lunkai Zhang, Diana Franklin, Frederic T. Chong. 247-257 [doi]
- Instruction Offloading with HMC 2.0 Standard: A Case Study for Graph TraversalsLifeng Nai, Hyesoon Kim. 258-261 [doi]
- Energy Efficient Scale-In Clusters with In-Storage Processing for Big-Data AnalyticsI. Stephen Choi, Yang-Suk Kee. 265-273 [doi]
- NCAM: Near-Data Processing for Nearest Neighbor SearchCarlo C. del Mundo, Vincent T. Lee, Luis Ceze, Mark Oskin. 274-275 [doi]
- Understanding Energy Aspects of Processing-near-Memory for HPC WorkloadsHyojong Kim, Hyesoon Kim, Sudhakar Yalamanchili, Arun F. Rodrigues. 276-282 [doi]
- Near memory data structure rearrangementMaya Gokhale, G. Scott Lloyd, Chris Hajas. 283-290 [doi]