Peer Johannsen - researchr alias

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Viewing Publication 1 - 5 from 5

2002

Speeding up hardware verification by automated data path scalingPeer Johannsen. PhD thesis, University of Kiel, 2002. [doi]

2001

BooStER: Speeding Up RTL Property Checking of Digital Designs by Word-Level AbstarctionPeer Johannsen. cav 2001: 373-377 [doi]

Reducing bitvector satisfiability problems to scale down design sizes for RTL property checkingPeer Johannsen. hldvt 2001: 123-128 [doi]

Utilizing High-Level Information for Formal Hardware VerificationPeer Johannsen, Rolf Drechsler. acs2 2002: 419-431 [doi]

Speeding Up Verification of RTL Designs by Computing One-to-one Abstractions with Reduced Signal WidthsPeer Johannsen, Rolf Drechsler. ifip10-5 2002: 361-374

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