Razieh Ghasemi - researchr alias

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Viewing Publication 1 - 6 from 6

2024

A Low-Power 10-Bit 2GS/s Hybrid Time-Interleaved Digital-to-Analog Converter with a New Neutrolized-Glitch Unit Current Cell in 65 nm CMOS TechnologyRazieh Ghasemi, Mohammad Azim Karami. cssp, 43(12):7472-7497, December 2024. [doi]

A low phase noise quadrature VCO using super-harmonic coupling technique in 65-nm CMOS technologyRazieh Ghasemi, Mohammad Azim Karami. ijcta, 52(1):97-110, January 2024. [doi]

2023

Efficient and optimized approximate GDI full adders based on dynamic threshold CNTFETs for specific least significant bitsAyoub Sadeghi, Razieh Ghasemi, Hossein Ghasemian, Nabiollah Shiri. jzusc, 24(4):599-616, 2023. [doi]

High Efficient GDI-CNTFET-Based Approximate Full Adder for Next Generation of Computer ArchitecturesAyoub Sadeghi, Razieh Ghasemi, Hossein Ghasemian, Nabiollah Shiri. esl, 15(1):33-36, March 2023. [doi]

2022

A 10-bit 1GSample/s hybrid digital-to-analog converter with a modified thermometer decoder in 65-nm CMOS technologyRazieh Ghasemi, Mohammad Azim Karami. ijcta, 50(1):83-107, 2022. [doi]

2019

A novel high-speed low-power dynamic comparator with complementary differential input in 65 nm CMOS technologyHossein Ghasemian, Razieh Ghasemi, Ebrahim Abiri, Mohammad Reza Salehi. mj, 92, 2019. [doi]

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