Sherif Abdalla - researchr alias

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Viewing Publication 1 - 4 from 4

2017

A 0.5-9.5-GHz, 1.2-µs Lock-Time Fractional-N DPLL With ±1.25%UI Period Jitter in 16-nm CMOS for Dynamic Frequency and Core-Count ScalingFazil Ahmad, Greg Unruh, Amrutha Iyer, Pin-en Su, Sherif Abdalla, Bo Shen, Mark Chambers, Ichiro Fujimori. jssc, 52(1):21-32, 2017. [doi]

2016

19.1 A 0.5-to-9.5GHz 1.2µs-lock-time fractional-N DPLL with ±1.25% UI period jitter in 16nm CMOS for dynamic frequency and core-count scaling in SoCFazil Ahmad, Greg Unruh, Amrutha Iyer, Pin-en Su, Sherif Abdalla, Bo Shen, Mark Chambers, Ichiro Fujimori. isscc 2016: 324-325 [doi]

2010

10Gb/s 15mW optical receiver with integrated Germanium photodetector and hybrid inductor peaking in 0.13µm SOI CMOS technologyDaniel Kucharski, Drew Guckenberger, Gianlorenzo Masini, Sherif Abdalla, J. Witzens, Subal Sahni. isscc 2010: 360-361 [doi]

2007

A Fully Integrated 4 × 10-Gb/s DWDM Optoelectronic Transceiver Implemented in a Standard 0.13 µm CMOS SOI TechnologyAdithyaram Narasimha, Behnam Analui, Yi Liang, Thomas J. Sleboda, Sherif Abdalla, Erwin Balmater, Steffen Gloeckner, Drew Guckenberger, Mark Harrison, Roger G. M. P. Koumans, Daniel Kucharski, Attila Mekis, Sina Mirsaidi, Dan Song, Thierry Pinguet. jssc, 42(12):2736-2744, 2007. [doi]

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