Victor Navarro-Botello - researchr alias

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Viewing Publication 1 - 5 from 5

2014

Analysis and optimization of dynamically reconfigurable regenerative comparators for ultra-low power 6-bit TC-ADCs in 90 nm CMOS technologiesJuan A. Montiel-Nelson, Victor Navarro-Botello, Javier Sosa, Tomás Bautista. mj, 45(10):1247-1253, 2014. [doi]

2009

A geometric approach to register transfer level satisfiabilityHéctor Navarro, Saeid Nooshabadi, Juan A. Montiel-Nelson, Victor Navarro-Botello, J. Sosa, José C. García. isqed 2009: 272-275 [doi]

2007

Analysis of High-Performance Fast Feedthrough Logic Families in CMOSVictor Navarro-Botello, Juan A. Montiel-Nelson, Saeid Nooshabadi. tcas, 54-II(6):489-493, 2007. [doi]

High performance low power CMOS dynamic logic for arithmetic circuitsVictor Navarro-Botello, Juan A. Montiel-Nelson, Saeid Nooshabadi. mj, 38(4-5):482-488, 2007. [doi]

2006

Low Power and High Performance Arithmetic Circuits in Feedthrough CMOS Logic Family for Low Power ApplicationsVictor Navarro-Botello, Juan A. Montiel-Nelson, Saeid Nooshabadi. jolpe, 2(2):300-307, 2006. [doi]

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