| 6 | -- | 8 | W. Kent Fuchs, Earl E. Swartzlander Jr.. Wafer-Scale Integration: Architectures and Algorithms - Guest Editors Introduction |
| 10 | -- | 18 | Robert W. Horst. Task-Flow Architecture for WSI Parallel Processing |
| 19 | -- | 27 | Koichi Yamashita, Shohei Ikehara. A Design and Yield Evaluation Technique for Wafer-Scale Memory |
| 29 | -- | 39 | Ahmed Boubekeur, Jean-Luc Patry, Gabriele Saucier, Jacques Trilhe. Configuring a Wafer-Scale Two-Dimensional Array of Single-Bit Processors |
| 41 | -- | 47 | Allan H. Anderson, Jack I. Raffel, Peter W. Wyatt. Wafer-Scale Integration Using Restructurable VLSI |
| 50 | -- | 56 | Glenn H. Chapman, M. Parameswaran, Marek Syrzycki. Wafer-Scale Transducer Arrays |
| 58 | -- | 65 | Wojciech Maly. Prospects for WSI: A Manufacturing Perspective |
| 66 | -- | 71 | David L. Landis, Nitin Nigam, Joseph W. Yoder. Wafer-Scale Optimization Using Computational Availability |
| 71 | -- | 75 | Vijay K. Jain, Hiroomi Hikawa, David C. Keezer. An Architecture for WSI Rapid Prototyping |