Journal: IEEE Design & Test of Computers

Volume 18, Issue 4

0 -- 0Todd M. Austin. Design for Verification?
2 -- 0Yervant Zorian. Error-Free Products
4 -- 5Carl Pixley. Guest Editor s Introduction: Formal Verification of Commercial Integrated Circuits
6 -- 15Harry Foster. Applied Boolean Equivalence Verification and RTL Static Sign-Off
16 -- 25Robert B. Jones, John W. O Leary, Carl-Johan H. Seger, Mark Aagaard, Thomas F. Melham. Practical Formal Verification in Microprocessor Design
26 -- 35Narayanan Krishnamurthy, Magdy S. Abadir, Andrew K. Martin, Jacob A. Abraham. Design and Development Paradigm for Industrial Formal Verification CAD Tools
36 -- 45Serdar Tasiran, Kurt Keutzer. Coverage Metrics for Functional Validation of Hardware Designs
46 -- 55Lionel Bening, Harry Foster. Optimizing Multiple EDA Tools within the ASIC Design Flow
56 -- 64Roberto d Amore, Osamu Saotome, Karl Heinz Kienitz. A Two-Input, One-Output Bit-Scalable Architecture for Fuzzy Processors
65 -- 71. Roundtable: Adding Reconfigurable Logic to SOC Designs
72 -- 0. Conference Reports
77 -- 0. DATC Newsletter
78 -- 79. TTCC Newsletter