External Links

    Journal: IEEE Design & Test of Computers

    Volume 18, Issue 6

    3 -- 0. EIC Message
    4 -- 5William H. Joyner Jr., Andrew B. Kahng. Guest Editor s Introduction: Roadmaps and Visions for Design and Test
    6 -- 11. Perspectives
    12 -- 22Dennis Sylvester, Himanshu Kaul. Power-Driven Challenges in Nanometer Design
    23 -- 33Alberto L. Sangiovanni-Vincentelli, Grant Martin. Platform-Based Design and Software Design Methodology for Embedded Systems
    34 -- 46Ralf Brederlow, Werner Weber, Joseph Sauerer, Stéphane Donnay, Piet Wambacq, Maarten Vertregt. A Mixed-Signal Design Roadmap
    47 -- 54Rohit Kapur, R. Chandramouli, Thomas W. Williams. Strategies for Low-Cost Test
    56 -- 62Kevin Stanley. High-Accuracy Flush-and-Scan Software Diagnostic
    70 -- 79. Annual Index
    80 -- 0. The Last Byte

    Volume 18, Issue 5

    0 -- 0Tom Anderson. Your Core-My Problem? Integration and Verification of IP
    1 -- 0Yervant Zorian. EIC Message
    5 -- 6. News
    7 -- 0Wayne Wolf, Ahmed Amine Jerraya. Application-Specific System-on-a-Chip Multiprocessors
    8 -- 20Wander O. Cesário, Gabriela Nicolescu, Lovic Gauthier, Damien Lyonnard, Ahmed Amine Jerraya. Colif: A Design Representation for Application-Specific Multiprocessor SOCs
    21 -- 31Santanu Dutta, Rune Jensen, Alf Rieckmann. Viper: A Multiprocessor SOC for Advanced Set-Top Box and Digital TV Systems
    32 -- 45Reinaldo A. Bergamaschi, Subhrajit Bhattacharya, Ronoldo Wagner, Colleen Fellenz, Michael Muhlada, William R. Lee, Foster White, Jean-Marc Daveau. Automating the Design of SOCs Using Cores
    46 -- 58Peng Yang, Chun Wong, Paul Marchal, Francky Catthoor, Dirk Desmet, Diederik Verkest, Rudy Lauwereins. Energy-Aware Runtime Scheduling for Embedded-Multiprocessor SOCs
    59 -- 0Tony Ambler, Donald L. Wheater. Test Trade-Offs Take Center Stage at ITC
    60 -- 69Jay Bedsole, Rajesh Raina, Al Crouch, Magdy S. Abadir. Very Low Cost Testers: Opportunities and Challenges
    70 -- 79Louis Y. Ungar, Tony Ambler. Economics of Built-in Self-Test
    80 -- 91Anshuman Chandra, Krishnendu Chakrabarty. Test Resource Partitioning for SOCs
    92 -- 99Alfredo Benso, Silvia Chiusano, Giorgio Di Natale, Paolo Prinetto, Monica Lobetti Bodoni. Online and Offline BIST in IP-Core Design
    100 -- 110Sérgio Akira Ito, Luigi Carro, Ricardo Pezzuol Jacobi. Making Java Work for Microcontroller Applications
    112 -- 119. Design Closure with Cell-Based Synthesis
    120 -- 0. Technology Continuous Education
    122 -- 123Peter J. Ashenden. VHDL Standards
    124 -- 0. New Products
    125 -- 0. DATC Newsletter
    126 -- 127. TTTC Newsletter
    128 -- 0Tony Ambler. Test Strategies and Marriage Partners

    Volume 18, Issue 4

    0 -- 0Todd M. Austin. Design for Verification?
    2 -- 0Yervant Zorian. Error-Free Products
    4 -- 5Carl Pixley. Guest Editor s Introduction: Formal Verification of Commercial Integrated Circuits
    6 -- 15Harry Foster. Applied Boolean Equivalence Verification and RTL Static Sign-Off
    16 -- 25Robert B. Jones, John W. O Leary, Carl-Johan H. Seger, Mark Aagaard, Thomas F. Melham. Practical Formal Verification in Microprocessor Design
    26 -- 35Narayanan Krishnamurthy, Magdy S. Abadir, Andrew K. Martin, Jacob A. Abraham. Design and Development Paradigm for Industrial Formal Verification CAD Tools
    36 -- 45Serdar Tasiran, Kurt Keutzer. Coverage Metrics for Functional Validation of Hardware Designs
    46 -- 55Lionel Bening, Harry Foster. Optimizing Multiple EDA Tools within the ASIC Design Flow
    56 -- 64Roberto d Amore, Osamu Saotome, Karl Heinz Kienitz. A Two-Input, One-Output Bit-Scalable Architecture for Fuzzy Processors
    65 -- 71. Roundtable: Adding Reconfigurable Logic to SOC Designs
    72 -- 0. Conference Reports
    77 -- 0. DATC Newsletter
    78 -- 79. TTCC Newsletter

    Volume 18, Issue 3

    1 -- 0Yervant Zorian. Huge Storage Capacity
    3 -- 4Rochit Rajsuman, Francky Catthoor. Guest Editors Intoduction: The New World of Large Embedded Memories
    5 -- 6Alex Shubat. Moving the Market to Embedded Memory
    7 -- 15Doris Keitel-Schulz, Norbert Wehn. Embedded DRAM Development: Technology, Physical Design, and Application Issues
    16 -- 27Rochit Rajsuman. Design and Test of Large Embedded Memories: An Overview
    28 -- 39Julie Segal, Alvin Jee, David Y. Lepejian, Ben Chu. Using Electrical Bitmap Results from Embedded Memory to Enhance Yield
    40 -- 54Lode Nachtergaele, Francky Catthoor, Chidamber Kulkarni. Random-Access Data Storage Components in Customized Architectures
    56 -- 68Preeti Ranjan Panda, Nikil D. Dutt, Alexandru Nicolau, Francky Catthoor, Arnout Vandecappelle, Erik Brockmeyer, Chidamber Kulkarni, Eddy de Greef. Data Memory Organization and Optimizations in Application-Specific Systems
    70 -- 82Francky Catthoor, Koen Danckaert, Sven Wuytack, Nikil D. Dutt. Code Transformations for Data Transfer and Storage Exploration Preprocessing in Multimedia Processors
    83 -- 97Kamran Zarrineh, Shambhu J. Upadhyaya, Vivek Chickermane. System-on-Chip Testability Using LSSD Scan Structures
    98 -- 107Margarida F. Jacome, Helvio P. Peixoto. A Survey of Digital Design Reuse
    108 -- 114Michael Sprachmann. Automatic Generation of Parallel CRC Circuits
    115 -- 123. A D&T Roundtable: System-on-Chip Specification and Modeling Using C++: Challenges and Opportunities
    127 -- 0. DATC Newsletter
    128 -- 0Ahmed Amine Jerraya. Two Enduring Questions for Computer Design

    Volume 18, Issue 2

    1 -- 0. Managing Power
    6 -- 9Enrico Macii. Guest Editor s Introduction: Dynamic Power Management of Electronic Systems
    10 -- 19Yung-Hsiang Lu, Giovanni De Micheli. Comparing System-Level Power Management Policies
    20 -- 30Dongkun Shin, Jihong Kim, Seongsoo Lee. Intra-Task Voltage Scheduling for Low-Energy, Hard Real-Time Applications
    31 -- 41Takanori Okuma, Hiroto Yasuura, Tohru Ishihara. Software Energy Reduction Techniques for Variable-Voltage Processors
    42 -- 52Stephen B. Furber, Aristides Efthymiou, Jim D. Garside, David W. Lloyd, Mike J. G. Lewis, Steve Temple. Power Management in the Amulet Microprocessors
    53 -- 60Luca Benini, Giuliano Castelli, Alberto Macii, Riccardo Scarsi. Battery-Driven Dynamic Power Management
    62 -- 74Amit Sinha, Anantha Chandrakasan. Dynamic Power Management in Wireless Sensor Networks
    76 -- 84Manoj Sachdev. Current-Based Testing for Deep-Submicron VLSIs
    86 -- 91. Panel Summaries
    92 -- 94. Conference Reports
    95 -- 0. Standards
    98 -- 105. A D&T Roundtable: Industrial and University Test Research Collaboration
    109 -- 110. TTTC Newsletter
    111 -- 0. DATC Newsletter
    112 -- 0Scott Davidson. Welcome to 2001

    Volume 18, Issue 1

    1 -- 0. D&T and the Future
    5 -- 7. News
    8 -- 9Fabrizio Lombardi, Cecilia Metra. Guest Editors Introduction: Defect-Oriented Diagnosis for Very Deep-Submicron Systems
    10 -- 18Jien-Chung Lo, William D. Armitage, Corbet S. Johnson. Using Atomic Force Microscopy for Deep-Submicron Failure Analysis
    19 -- 30Srikanth Venkataraman, Scott Brady Drummonds. Poirot: Applications of a Logic Fault Diagnosis Tool
    31 -- 41Jennifer Dworak, Jason D. Wicker, Sooryong Lee, Michael R. Grimaila, M. Ray Mercer, Kenneth M. Butler, Bret Stewart, Li-C. Wang. Defect-Oriented Testing and Defective-Part-Level Prediction
    42 -- 49Khurram Muhammad, Kaushik Roy. Fault Detection and Location Using IDD Waveform Analysis
    50 -- 61Jim Plusquellic. IC Diagnosis Using Multiple Supply Pad IDDQs
    63 -- 71David San Segundo Bello, Ronald J. W. T. Tangelder, Hans G. Kerkhoff. Modeling a Verification Test System for Mixed-Signal Circuits
    72 -- 81Mani Soma, Sam D. Huynh, Jinyan Zhang, Seongwon Kim, Giri Devarayanadurg. Hierarchical ATPG for Analog Circuits and Systems
    82 -- 89. A D&T Roundtable: Are Single-Chip Multiprocessors in Reach?
    90 -- 92. Panel Summaries
    93 -- 0. Conference Reports
    94 -- 0. DATC Newsletter
    95 -- 0. TTTC Newsletter
    96 -- 0. Danger! Submicron Defects!
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