Journal: IEEE Design & Test of Computers

Volume 22, Issue 5

393 -- 0Rajesh K. Gupta. On-chip networks
397 -- 398Grant Martin. Wireless, ESL, DFM, and Power on Stage at 42nd DAC
399 -- 403André Ivanov, Giovanni De Micheli. Guest Editors Introduction: The Network-on-Chip Paradigm in Practice and Research
404 -- 413Partha Pratim Pande, Cristian Grecu, André Ivanov, Resve A. Saleh, Giovanni De Micheli. Design, Synthesis, and Test of Networks on Chips
414 -- 421Kees Goossens, John Dielissen, Andrei Radulescu. Æthereal Network on Chip: Concepts, Architectures, and Implementations
422 -- 433Se-Joong Lee, Kangmin Lee, Hoi-Jun Yoo. Analysis and Implementation of Practical, Cost-Effective Networks on Chips
434 -- 442Srinivasan Murali, Theo Theocharides, Narayanan Vijaykrishnan, Mary Jane Irwin, Luca Benini, Giovanni De Micheli. Analysis of Error Recovery Schemes for Networks on Chips
443 -- 451Christophe Bobda, Ali Ahmadinia. Dynamic Interconnection of Reconfigurable Modules on Reconfigurable Devices
452 -- 460Javier Resano, Daniel Mozos, Diederik Verkest, Francky Catthoor. A Reconfiguration Manager for Dynamically Reconfigurable Hardware
462 -- 471Braulio Adriano de Mello, Uilian Rafael Feijo Souza, Josue Klafke Sperb, Flávio Rech Wagner. Tangram: Virtual Integration of IP Components in a Distributed Cosimulation
472 -- 477. Inventions: A Result of Risk-Taking, Diversity, and Holistic Thinking - An interview with Bernard S. Meyerson, IBM Fellow, Vice President, and Chief Technologist of IBM s System Technology Group
478 -- 479Grant Martin. Verification by the pound
480 -- 481. Conference Reports
482 -- 483. Panel Summaries
484 -- 486Victor Berman. An update on IEEE P1647: The e system verification language
487 -- 0. DATC Newsletter
488 -- 0Resve A. Saleh. An approach that will NoC your SoCs off!