Journal: IEEE Design & Test of Computers

Volume 22, Issue 6

493 -- 494Rajesh K. Gupta. Going 3D: Silicon and D&T
496 -- 497Sachin S. Sapatnekar, Kevin J. Nowka. Guest Editors Introduction: New Dimensions in 3D Integration
498 -- 510W. Rhett Davis, John Wilson, Stephen Mick, Jian Xu, Hao Hua, Christopher Mineo, Ambarish M. Sule, Michael Steer, Paul D. Franzon. Demystifying 3D ICs: The Pros and Cons of Going Vertical
512 -- 518Peter Benkart, Alexander Kaiser, Andreas Munding, Markus Bschorr, Hans-Jörg Pfleiderer, Erhard Kohn, Arne Heittmann, Holger Huebner, Ulrich Ramacher. 3D Chip Stack Technology Using Through-Chip Interconnects
520 -- 531Cristinel Ababei, Yan Feng, Brent Goplen, Hushrav Mogal, Tianpei Zhang, Kia Bazargan, Sachin S. Sapatnekar. Placement and Routing in 3D Integrated Circuits
532 -- 539Sung Kyu Lim. Physical Design for 3D System on Package
540 -- 547Philip Jacob, Okan Erdogan, Aamir Zia, Paul M. Belemjian, Russell P. Kraft, John F. McDonald. Predicting the Performance of a 3D Processor-Memory Chip Stack
548 -- 555Annie (Yujuan) Zeng, James (JianQiang) Lü, Kenneth Rose, Ronald J. Gutmann. First-Order Performance Prediction of Cache Memory with Wafer-Level3D Integration
556 -- 564Christianto C. Liu, Ilya Ganusov, Martin Burtscher, Sandip Tiwari. Bridging the Processor-Memory Performance Gapwith 3D IC Technology
565 -- 0Scott Davidson. Guest Editor s Introduction: ITC Examines How Test Helps the Fittest Survive
566 -- 574Subhasish Mitra, Steven S. Lumetta, Michael Mitzenmacher, Nishant Patil. X-Tolerant Test Response Compaction
576 -- 584Xiao Liu, Michael S. Hsiao. A Novel Transition Fault ATPG That Reduces Yield Loss
586 -- 595Sagar S. Sabade, Duncan M. Walker. IC Outlier Identification Using Multiple Test Metrics
596 -- 597Sachin S. Sapatnekar. Designing Vary Good Circuitry
598 -- 599. Panel Summaries
600 -- 0Vladimir Hahanov. 2005 IEEE East-West Design and Test Workshop
616 -- 0Robert C. Aitken. ITC is Cool

Volume 22, Issue 5

393 -- 0Rajesh K. Gupta. On-chip networks
397 -- 398Grant Martin. Wireless, ESL, DFM, and Power on Stage at 42nd DAC
399 -- 403André Ivanov, Giovanni De Micheli. Guest Editors Introduction: The Network-on-Chip Paradigm in Practice and Research
404 -- 413Partha Pratim Pande, Cristian Grecu, André Ivanov, Resve A. Saleh, Giovanni De Micheli. Design, Synthesis, and Test of Networks on Chips
414 -- 421Kees Goossens, John Dielissen, Andrei Radulescu. Æthereal Network on Chip: Concepts, Architectures, and Implementations
422 -- 433Se-Joong Lee, Kangmin Lee, Hoi-Jun Yoo. Analysis and Implementation of Practical, Cost-Effective Networks on Chips
434 -- 442Srinivasan Murali, Theo Theocharides, Narayanan Vijaykrishnan, Mary Jane Irwin, Luca Benini, Giovanni De Micheli. Analysis of Error Recovery Schemes for Networks on Chips
443 -- 451Christophe Bobda, Ali Ahmadinia. Dynamic Interconnection of Reconfigurable Modules on Reconfigurable Devices
452 -- 460Javier Resano, Daniel Mozos, Diederik Verkest, Francky Catthoor. A Reconfiguration Manager for Dynamically Reconfigurable Hardware
462 -- 471Braulio Adriano de Mello, Uilian Rafael Feijo Souza, Josue Klafke Sperb, Flávio Rech Wagner. Tangram: Virtual Integration of IP Components in a Distributed Cosimulation
472 -- 477. Inventions: A Result of Risk-Taking, Diversity, and Holistic Thinking - An interview with Bernard S. Meyerson, IBM Fellow, Vice President, and Chief Technologist of IBM s System Technology Group
478 -- 479Grant Martin. Verification by the pound
480 -- 481. Conference Reports
482 -- 483. Panel Summaries
484 -- 486Victor Berman. An update on IEEE P1647: The e system verification language
487 -- 0. DATC Newsletter
488 -- 0Resve A. Saleh. An approach that will NoC your SoCs off!

Volume 22, Issue 4

0 -- 0Rajesh K. Gupta. Nanotechnology: Where science of the small meets math of the large
0 -- 0Luigi Carro. Adding value to design and test through education: What are the challenges?
293 -- 294Giovanni De Micheli, Al Dunlop. IEEE Council for Electronic Design Automation: A new beginning
295 -- 297R. Iris Bahar, Mehdi Baradaran Tahoori, Sandeep K. Shukla, Fabrizio Lombardi. Guest Editors Introduction: Challenges for Reliable Design at the Nanoscale
298 -- 305Darshan D. Thaker, Francois Impens, Isaac L. Chuang, Rajeevan Amirtharajah, Frederic T. Chong. Recursive TMR: Scaling Fault Tolerance in the Nanoscale Era
306 -- 315André DeHon, Helia Naeimi. Seven Strategies for Tolerating Highly Defective Fabrication
316 -- 326Chen He, Margarida F. Jacome, Gustavo de Veciana. A Reconfiguration-Based Defect-Tolerant Design Paradigm for Nanotechnologies
328 -- 339Jie Han, Jianbo Gao, Yan Qi 0003, Pieter Jonker, José A. B. Fortes. Toward Hardware-Redundant, Fault-Tolerant Logic for Nanoelectronics
340 -- 348Daniele Rossi, André K. Nieuwland, Atul Katoch, Cecilia Metra. New ECC for Crosstalk Impact Minimization
349 -- 361Mark L. Chang, Scott Hauck. Précis: A Usercentric Word-Length Optimization Tool
362 -- 375Chong Zhao, Sujit Dey, Xiaoliang Bai. Soft-Spot Analysis: Targeting Compound Noise Effects in Nanometer Circuits
376 -- 385Rajeev R. Rao, David Blaauw, Dennis Sylvester, Anirudh Devgan. Modeling and Analysis of Parametric Yield under Power and Performance Constraints
386 -- 387Scott Davidson. BIST the hard way
392 -- 0Scott Davidson. What s the problem?

Volume 22, Issue 3

0 -- 0Thomas W. Williams. TTTC recognizes test visionary s lifetime contribution
193 -- 0Rajesh K. Gupta. The other face of design for manufacturability
197 -- 199Andrew B. Kahng, Grant Martin. DAC Highlights
200 -- 205Juan Antonio Carballo, Yervant Zorian, Raul Camposano, Andrzej J. Strojwas, John Kibarian, Dennis Wassung, Alex Alexanian, Steve Wigley, Neil Kelly. Guest Editors Introduction: DFM Drives Changes in Design Flow
206 -- 213Alfred K. Wong. Some Thoughts on the IC Design-Manufacture Interface
214 -- 222Jeng-Liang Tsai, Dong Hyun Baik, Charlie Chung-Ping Chen, Kewal K. Saluja. Yield-Driven, False-Path-Aware Clock Skew Scheduling
224 -- 231Jay Jahangiri, David Abercrombie. Value-Added Defect Testing Techniques
232 -- 239Greg Yeric, Ethan Cohen, John Garcia, Kurt Davis, Esam Salem, Gary Green. Infrastructure for Successful BEOL Yield Ramp, Transfer to Manufacturing, and DFM Characterization at 65 nm and Below
240 -- 246Robert Madge. New test paradigms for yield and manufacturability
248 -- 257Maher N. Mneimneh, Karem A. Sakallah. Principles of Sequential-Equivalence Verification
258 -- 266Robert Baumann. Soft Errors in Advanced Computer Systems
268 -- 279. The Future Depends on Innovation: An Interview with Irwin M. Jacobs, cofounder, chairman, and CEO of Qualcomm
280 -- 281Sachin S. Sapatnekar. Empowering the designer
283 -- 285Victor Berman. IEEE P1647 and P1800: Two approaches to standardization and language design
286 -- 0. Design Automation Technical Committee Newsletter
288 -- 0Gary Smith. Design for manufacturability comes of age

Volume 22, Issue 2

81 -- 0Rajesh K. Gupta. FPGA-enabled computing architectures
85 -- 89Patrick Lysaght, P. A. Subrahmanyam. Guest Editors Introduction: Advances in Configurable Computing
90 -- 101Bingfeng Mei, Andy Lambrechts, Diederik Verkest, Jean-Yves Mignolet, Rudy Lauwereins. Architecture Exploration for a Reconfigurable Architecture Template
102 -- 113Miljan Vuletic, Laura Pozzi, Paolo Ienne. Seamless Hardware-Software Integration in Reconfigurable Computing Systems
114 -- 125Chen Chang, John Wawrzynek, Robert W. Brodersen. BEE2: A High-End Reconfigurable Computing System
126 -- 134Daniel T. Hamling. Test Solution Selection Using Multiple-Objective Decision Models and Analyses
136 -- 148Jürgen Becker, Alexander Thomas. Scalable Processor Instruction Set Extension
150 -- 159Chulsung Park, Jinfeng Liu, Pai H. Chou. B#: A Battery Emulator and Power-Profiling Instrument
160 -- 169Ming Shae Wu, Chung-Len Lee. Using a Periodic Square Wave Test Signal to Detect Crosstalk Faults
170 -- 180Ken Wagner, Patrick P. Gelsinger. Driving the 5 Billion Innovation Engine at Intel: An Interview with Patrick P. Gelsinger, Digital Enterprise Group Senior Vice President and General Manager, Intel
182 -- 183Victor Berman. Sharing standards work with Japan
184 -- 185Grant Martin. The network is the chip
186 -- 189Carol Stolicny. ITC 2004 panels: Part 1
190 -- 0. DATC Newsletter
192 -- 0Tom Kean. Déjà vu, all over again

Volume 22, Issue 1

5 -- 6Rajesh K. Gupta. Global competitiveness, outsourcing, and education in the semiconductor industry
7 -- 9Kenneth D. Wagner. Keeping current with silicon and systems technology in the mid-90s
10 -- 11Stephen H. Unger. Is engineering a viable profession in the US?
12 -- 13T. J. Rodgers. The truth about outsourcing
14 -- 16Alberto L. Sangiovanni-Vincentelli. The importance of innovation in the economy of advanced countries
17 -- 0R. Chandramouli. Infrastructure IP design for repair in nanometer technologies
18 -- 26Tiehan Lv, Jiang Xu, Wayne Wolf, Burak Ozer, Jörg Henkel, Srimat T. Chakradhar. A Methodology for Architectural Design of Multimedia Multiprocessor SoCs
28 -- 38. Software Development for High-Performance, Reconfigurable, Embedded Multimedia Systems
39 -- 49Brian Delaney, Tajana Simunic, Nikil Jayant. Energy-Aware Distributed Speech Recognition for Wireless Mobile Devices
50 -- 58Gustavo Neuberger, Fernanda Gusmão de Lima Kastensmidt, Ricardo Reis. An Automatic Technique for Optimizing Reed-Solomon Codes to Improve Fault Tolerance in Memories
59 -- 70Daniele Rossi, André K. Nieuwland, Atul Katoch, Cecilia Metra. Exploiting ECC Redundancy to Minimize Crosstalk Impact
71 -- 73Victor Berman. Is it time to reexamine patent policy for standards?
74 -- 75Sachin S. Sapatnekar. An EDA compendium
76 -- 78. Conference Reports
79 -- 0. DATC Newsletter
80 -- 0Scott Davidson. Testing: It s not just pass/fail anymore