| 508 | -- | 0 | Tim Cheng. Design and test for reliability and efficiency |
| 510 | -- | 519 | Reinaldo A. Bergamaschi, Luca Benini, Krisztián Flautner, Wido Kruijtzer, Alberto L. Sangiovanni-Vincentelli, Kazutoshi Wakabayashi. The State of ESL Design [Roundtable] |
| 520 | -- | 526 | Rajesh Gupta, Arvind, Gérard Berry, Forrest Brewer. Advances in ESL Design |
| 528 | -- | 537 | William R. Mann. Wafer Test Methods to Improve Semiconductor Die Reliability |
| 538 | -- | 548 | Dimitrios Simos, Ioannis Papaefstathiou, Manolis Katevenis. Building an FoC Using Large, Buffered Crossbar Cores |
| 549 | -- | 559 | Mohammad Tehranipoor, Reza M. Rad. Defect Tolerance for Nanoscale Crossbar-Based Devices |
| 560 | -- | 570 | Jen-Chieh Yeh, Chao-Hsun Chen, Cheng-Wen Wu, Shuo-Fen Kuo. A Systematic Approach to Memory Test Time Reduction |
| 572 | -- | 580 | Abbas Sheibanyrad, Alain Greiner, Ivan Miro Panades. Multisynchronous and Fully Asynchronous NoCs for GALS Architectures |
| 581 | -- | 589 | Stefan Valentin Gheorghita, Twan Basten, Henk Corporaal. Application Scenarios in Streaming-Oriented Embedded-System Design |
| 590 | -- | 598 | Ted Huffmire, Brett Brotherton, Timothy Sherwood, Ryan Kastner, Timothy E. Levin, Thuy D. Nguyen, Cynthia E. Irvine. Managing Security in FPGA-Based Embedded Systems |
| 600 | -- | 601 | Grant Martin. The two faces of high-level synthesis [review of High-Level Synthesis: From Algorithm to Digital Circuit (Coussy, P. and Morawiec, A., Eds., 2008)] |
| 608 | -- | 609 | Melvin A. Breuer. Clarifying the record on testability cost functions |