Journal: IEEE Design & Test of Computers

Volume 25, Issue 6

508 -- 0Tim Cheng. Design and test for reliability and efficiency
510 -- 519Reinaldo A. Bergamaschi, Luca Benini, Krisztián Flautner, Wido Kruijtzer, Alberto L. Sangiovanni-Vincentelli, Kazutoshi Wakabayashi. The State of ESL Design [Roundtable]
520 -- 526Rajesh Gupta, Arvind, Gérard Berry, Forrest Brewer. Advances in ESL Design
528 -- 537William R. Mann. Wafer Test Methods to Improve Semiconductor Die Reliability
538 -- 548Dimitrios Simos, Ioannis Papaefstathiou, Manolis Katevenis. Building an FoC Using Large, Buffered Crossbar Cores
549 -- 559Mohammad Tehranipoor, Reza M. Rad. Defect Tolerance for Nanoscale Crossbar-Based Devices
560 -- 570Jen-Chieh Yeh, Chao-Hsun Chen, Cheng-Wen Wu, Shuo-Fen Kuo. A Systematic Approach to Memory Test Time Reduction
572 -- 580Abbas Sheibanyrad, Alain Greiner, Ivan Miro Panades. Multisynchronous and Fully Asynchronous NoCs for GALS Architectures
581 -- 589Stefan Valentin Gheorghita, Twan Basten, Henk Corporaal. Application Scenarios in Streaming-Oriented Embedded-System Design
590 -- 598Ted Huffmire, Brett Brotherton, Timothy Sherwood, Ryan Kastner, Timothy E. Levin, Thuy D. Nguyen, Cynthia E. Irvine. Managing Security in FPGA-Based Embedded Systems
600 -- 601Grant Martin. The two faces of high-level synthesis [review of High-Level Synthesis: From Algorithm to Digital Circuit (Coussy, P. and Morawiec, A., Eds., 2008)]
608 -- 609Melvin A. Breuer. Clarifying the record on testability cost functions

Volume 25, Issue 5

398 -- 399Nur A. Touba. ITC 2008 Highlights
400 -- 401Yatin Vasant Hoskote, Radu Marculescu, Li-Shiuan Peh. Guest Editors Introduction: Tackling Key Problems in NoCs
402 -- 415Alessandro Pinto, Luca P. Carloni, Alberto L. Sangiovanni-Vincentelli. COSI: A Framework for the Design of Interconnection Networks
416 -- 428Stephan Bourduas, Jean-Samuel Chenard, Zeljko Zilic. A Quality-Driven Design Approach for NoCs
430 -- 439Byungsub Kim, Vladimir Stojanovic. Characterization of Equalized and Repeated Interconnects for NoC Applications
442 -- 451Matthias Kühnle, Michael Hübner, Jürgen Becker, Antonio Deledda, Claudio Mucci, Florian Ries, Marcello Coppola, Lorenzo Pieralisi, Riccardo Locatelli, Giuseppe Maruccia, Tommaso DeMarco, Fabio Campi. An Interconnect Strategy for a Heterogeneous, Reconfigurable SoC
452 -- 461Jorge Semião, Marcial Jesús Rodríguez-Irago, Juan J. Rodríguez-Andina, Leonardo Bisch Piccoli, Fabian Vargas, Marcelino Bicho Dos Santos, Isabel Maria Cacho Teixeira, João Paulo Teixeira. Signal Integrity Enhancement in Digital Circuits
462 -- 477Chung-Fu Kao, Hsin-Ming Chen, Ing-Jer Huang. Hardware-Software Approaches to In-Circuit Emulation for Embedded Processors
478 -- 486Geeng-Wei Lee, Juinn-Dar Huang, Chun-Yao Wang, Jing-Yang Jou. Verification of Pin-Accurate Port Connections
488 -- 494Giovanni De Micheli. Designing Micro- and Nanosystems for a Safer and Healthier Tomorrow
496 -- 497Sachin S. Sapatnekar. Adapting to the times [review of Adaptive Techniques for Dynamic Processor Optimization: Theory and Practice (Wang, A. and Naffziger, S., Eds.; 2008)]
504 -- 0Ian R. Mackintosh. OCP-IP NoC Benchmarking WG activities

Volume 25, Issue 4

292 -- 0Tim Cheng. Not just research as usual
294 -- 295William H. Joyner Jr., David C. Yeh. Guest Editors Introduction: System IC Design Challenges beyond 32 nm
296 -- 302Jan M. Rabaey, Sharad Malik. Challenges and Solutions for Late- and Post-Silicon Design
312 -- 320Wen-mei Hwu, Kurt Keutzer, Timothy G. Mattson. The Concurrency Challenge
321 -- 0Richard Oehler. The GSRC: Bridging Academia and Industry
322 -- 332Todd M. Austin, Valeria Bertacco, Scott A. Mahlke, Yu Cao. Reliable Systems on Unreliable Fabrics
333 -- 0Ajith Amerasekera. The Changing Design Landscape
334 -- 343Naresh R. Shanbhag, Subhasish Mitra, Gustavo de Veciana, Michael Orshansky, Radu Marculescu, Jaijeet Roychowdhury, Douglas L. Jones, Jan M. Rabaey. The Search for Alternative Computational Paradigms
344 -- 0Leon Stok. Variability and New Design Paradigms
346 -- 357Alberto L. Sangiovanni-Vincentelli. Is a Unified Methodology for System-Level Design Possible?
358 -- 365Jan M. Rabaey, Daniel Burke, Ken Lutz, John Wawrzynek. Workloads of the Future
366 -- 367John C. Zolper. The GSRC s Role in Meeting Tomorrow s Design Challenges
372 -- 381Philip Y. Paik, Vamsee K. Pamula, Krishnendu Chakrabarty. A Digital-Microfluidic Approach to Chip Cooling
382 -- 383Scott Davidson. With pick and shovel through our data
384 -- 0Joe Damore. DATC Newsletter
392 -- 0Betsy Weitzman. Who knew this experiment would be so successful?

Volume 25, Issue 3

204 -- 0Tim Cheng. Effective silicon debug is key for time to money
206 -- 207Rob Aitken, Erik Jan Marinissen. Guest Editors Introduction: Addressing the Challenges of Debug and Diagnosis
208 -- 215Bart Vermeulen. Functional Debug Techniques for Embedded Systems
216 -- 223Miron Abramovici. In-System Silicon Validation and Debug
224 -- 230. Case Study on Speed Failure Causes in a Microprocessor
232 -- 239Pouria Bastani, Li-C. Wang, Magdy S. Abadir. Linking Statistical Learning to Diagnosis
240 -- 248Yu Huang, Ruifeng Guo, Wu-Tung Cheng, James Chien-Mo Li. Survey of Scan Chain Diagnosis
250 -- 257Christian Boit, Rudolf Schlangen, Uwe Kerst, Ted Lundquist. Physical Techniques for Chip-Backside IC Debug in Nanotechnologies
258 -- 267Bart Vermeulen, Neal Stollon, Rolf Kühnis, Gary Swoboda, Jeff Rearick. Overview of Debug Standardization Activities
272 -- 278David Yeh, Li-Shiuan Peh, Shekhar Borkar, John A. Darringer, Anant Agarwal, Wen-mei Hwu. Thousand-Core Chips [Roundtable]
284 -- 285Grant Martin. Learning to assert yourself [review of Creating Assertion-Based IP (H.D. Foster and A.C. Krolnik; 2008)]
288 -- 0Erik Jan Marinissen. Bugs, moths, grasshoppers, and whales

Volume 25, Issue 2

105 -- 0Tim Cheng. Test compression saves bits, cycles, and money
112 -- 113Scott Davidson, Nur A. Touba. Guest Editors Introduction: Progress in Test Compression
114 -- 120Rohit Kapur, Subhasish Mitra, Thomas W. Williams. Historical Perspective on Scan Compression
122 -- 130Laung-Terng Wang, Xiaoqing Wen, Shianling Wu, Zhigang Wang, Zhigang Jiang, Boryau Sheu, Xinli Gu. VirtualScan: Test Compression Technology Using Combinational Logic and One-Pass ATPG
132 -- 140Chao-Wen Tzeng, Shi-Yu Huang. UMC-Scan Test Methodology: Exploiting the Maximum Freedom of Multicasting
142 -- 148Kee Sup Kim, Ming Zhang. Hierarchical Test Compression for SoC Designs
150 -- 159Ganesh Srinivasan, Friedrich Taenzler, Abhijit Chatterjee. Loopback DFT for Low-Cost Test of Single-VCO-Based Wireless Transceivers
160 -- 166Qizhang Yin, William R. Eisenstadt, Tian Xia. Wireless System for Microwave Test Signal Generation
168 -- 177Melvin A. Breuer, Haiyang (Henry) Zhu. An Illustrated Methodology for Analysis of Error Tolerance
178 -- 186Hamidreza Hashempour, Fabrizio Lombardi. Device Model for Ballistic CNFETs Using the First Conducting Band
187 -- 0Joe Damore. DATC Newsletter
192 -- 193Victor Berman. Standards update from IP 07
194 -- 195Sachin S. Sapatnekar. Building your yield of dreams
198 -- 199Bruce C. Kim. TTTC Newsletter
200 -- 0Scott Davidson. The commonality of vector generation techniques

Volume 25, Issue 1

4 -- 0Tim Cheng. From the EIC
6 -- 8Bruce C. Kim, Craig Force. Guest Editors Introduction: The Evolution of RFIC Design and Test
10 -- 16Vasanth Kakani, Fa Foster Dai. Design and Analysis of a Transversal Filter RFIC in SiGe Technology
18 -- 28Changwook Yoon, Junwoo Lee, Young-Jin Park, Hyunjeong Park, Jaemin Kim, Junso Pak, Joungho Kim. Design of a Low-Noise UWB Transceiver SiP
29 -- 37Yves Joannon, Vincent Beroulle, Chantal Robach, Smail Tedjini, Jean-Louis Carbonéro. Decreasing Test Qualification Time in AMS and RF Systems
38 -- 43Joe Kelly, Dean Nicholson, Edwin Lowery, Victor Grothen. Light-Enhanced FET Switch Improves ATE RF Power Settling
44 -- 51John Mark Nolen, Rabi N. Mahapatra. Time-Division-Multiplexed Test Delivery for NoC Systems
52 -- 62Jorgen Peddersen, Sri Parameswaran. Low-Impact Processor for Dynamic Runtime Power Management
64 -- 75Nektarios Kranitis, Andreas Merentitis, George Theodorou, Antonis M. Paschalis, Dimitris Gizopoulos. Hybrid-SBST Methodology for Efficient Testing of Processor Cores
76 -- 86Daniele Rossi, André K. Nieuwland, Cecilia Metra. Simultaneous Switching Noise: The Relation between Bus Layout and Coding
96 -- 98Scott Davidson. How to make your own processor architecture
102 -- 0Joe Damore. DATC Newsletter
103 -- 0Bruce C. Kim. TTTC Newsletter
104 -- 0William Krenik. Changing times in the RF world