| 2 | -- | 0 | . From the EIC: Building and verifying hardware at a higher level of abstraction |
| 4 | -- | 6 | Philippe Coussy, Andres Takach. Guest Editors Introduction: Raising the Abstraction Level of Hardware Design |
| 8 | -- | 17 | Philippe Coussy, Daniel D. Gajski, Michael Meredith, Andres Takach. An Introduction to High-Level Synthesis |
| 18 | -- | 25 | Grant Martin, Gary Smith. High-Level Synthesis: Past, Present, and Future |
| 26 | -- | 33 | . Virtual Roundtable: User Perspectives |
| 34 | -- | 45 | Soujanna Sarkar, Shashank Dabral, Praveen Tiwari, Raj S. Mitra. Lessons and Experiences with High-Level Synthesis |
| 46 | -- | 57 | Maciej J. Ciesielski, Jérémie Guillot, Daniel Gomez-Prado, Emmanuel Boutillon. High-Level Dataflow Transformations Using Taylor Expansion Diagrams |
| 58 | -- | 67 | Sumit Ahuja, Swathi T. Gurumani, Chad Spackman, Sandeep K. Shukla. Hardware Coprocessor Synthesis from an ANSI C Specification |
| 68 | -- | 77 | MarÃa C. Molina, Rafael Ruiz-Sautua, Alberto A. Del Barrio, Jose Manuel Mendias. Subword Switching Activity Minimization to Optimize Dynamic Power Consumption |
| 78 | -- | 87 | Yuan Xie, Yibo Chen. Statistical High-Level Synthesis under Process Variability |
| 88 | -- | 95 | Anmol Mathur, Masahiro Fujita, Edmund M. Clarke, Pascal Urard. Functional Equivalence Verification Tools in High-Level Synthesis Flows |
| 96 | -- | 98 | . CEDA Currents |
| 100 | -- | 101 | Igor L. Markov. Book Review: A physical-design picture book |
| 102 | -- | 103 | . Test Technology TC Newsletter |
| 104 | -- | 0 | Jason Cong, Wolfgang Rosenstiel. The Last Byte: The HLS tipping point |