Journal: IEEE Design & Test of Computers

Volume 26, Issue 6

2 -- 3. Design for reliability and robustness
6 -- 7Yu Cao, Jim Tschanz, Pradip Bose. Guest Editors Introduction: Reliability Challenges in Nano-CMOS Design
8 -- 17Sang Phill Park, Kunhyuk Kang, Kaushik Roy. Reliability Implications of Bias-Temperature Instability in Digital ICs
18 -- 27Muhammad Bashir, Linda Milor. Modeling Low-k Dielectric Breakdown to Determine Lifetime Requirements
28 -- 39Yanjing Li, Young Moon Kim, Evelyn Mintarno, Donald S. Gardner, Subhasish Mitra. Overcoming Early-Life Failure and Aging for Robust Systems
40 -- 49Prashant Singh, Cheng Zhuo, Eric Karl, David Blaauw, Dennis Sylvester. Sensor-Driven Reliability and Wearout Management
50 -- 61Dongwoo Lee, Jongwhoa Na. A Novel Simulation Fault Injection Method for Dependability Analysis
62 -- 73Jude A. Rivers, Prabhakar Kudva. Reliability Challenges and System Performance at the Architecture Level
74 -- 83Tero Vallius, Juha Röning. EOC: Electronic Building Blocks for Embedded Systems
84 -- 94Iakovos Mavroidis, Ioannis Mavroidis, Ioannis Papaefstathiou. Accelerating Emulation and Providing Full Chip Observability and Controllability
95 -- 0. Conference Reports
98 -- 99Scott Davidson. Book Reviews: A guide for the wrapper perplexed
102 -- 103. Design Automation Technical Committee Newsletter
104 -- 0Scott Davidson. The Last Byte: Too many reboots

Volume 26, Issue 5

4 -- 5David S. Kung, Yuan Xie. Guest Editors Introduction: Opportunities and Challenges of 3D Integration
6 -- 14Philip G. Emma, Eren Kursun. Opportunities and Challenges for 3D Systems and Their Design
15 -- 25Pingqiang Zhou, Karthikk Sridharan, Sachin S. Sapatnekar. Optimizing Decoupling Capacitors in 3D Circuits for Power Grid Integrity
26 -- 35Hsien-Hsin S. Lee, Krishnendu Chakrabarty. Test Challenges for 3D Integrated Circuits
36 -- 47Hongbin Sun, Jibang Liu, Rakesh S. Anigundi, Nanning Zheng, Jian-Qiang Lu, Kenneth Rose, Tong Zhang. 3D DRAM Design and Application to 3D Multicore Systems
48 -- 62Gordon W. Roberts, Sadok Aouini. Mixed-Signal Production Test: A Measurement Principle Perspective
64 -- 73W. Robert Daasch, Glenn Shirley, Amit Nahar. Statistics in Semiconductor Test: Going beyond Yield
74 -- 82Kenneth M. Butler, John M. Carulli Jr., Jayashree Saxena, Amit Nahar, W. Robert Daasch. Multidimensional Test Escape Rate Modeling
83 -- 91Martin Ruckert, Axel Böttcher, Martin Hauser. A Generic Virtual Bus for Hardware Simulator Composition
92 -- 104Hao Yu, Lei He, Mau-Chung Frank Chang. Robust On-Chip Signaling by Staggered and Twisted Bundle
106 -- 107Grant Martin. Teaching someone to fish
112 -- 0David S. Kung. The fate of stacking

Volume 26, Issue 4

2 -- 0. From the EIC: Building and verifying hardware at a higher level of abstraction
4 -- 6Philippe Coussy, Andres Takach. Guest Editors Introduction: Raising the Abstraction Level of Hardware Design
8 -- 17Philippe Coussy, Daniel D. Gajski, Michael Meredith, Andres Takach. An Introduction to High-Level Synthesis
18 -- 25Grant Martin, Gary Smith. High-Level Synthesis: Past, Present, and Future
26 -- 33. Virtual Roundtable: User Perspectives
34 -- 45Soujanna Sarkar, Shashank Dabral, Praveen Tiwari, Raj S. Mitra. Lessons and Experiences with High-Level Synthesis
46 -- 57Maciej J. Ciesielski, Jérémie Guillot, Daniel Gomez-Prado, Emmanuel Boutillon. High-Level Dataflow Transformations Using Taylor Expansion Diagrams
58 -- 67Sumit Ahuja, Swathi T. Gurumani, Chad Spackman, Sandeep K. Shukla. Hardware Coprocessor Synthesis from an ANSI C Specification
68 -- 77María C. Molina, Rafael Ruiz-Sautua, Alberto A. Del Barrio, Jose Manuel Mendias. Subword Switching Activity Minimization to Optimize Dynamic Power Consumption
78 -- 87Yuan Xie, Yibo Chen. Statistical High-Level Synthesis under Process Variability
88 -- 95Anmol Mathur, Masahiro Fujita, Edmund M. Clarke, Pascal Urard. Functional Equivalence Verification Tools in High-Level Synthesis Flows
96 -- 98. CEDA Currents
100 -- 101Igor L. Markov. Book Review: A physical-design picture book
102 -- 103. Test Technology TC Newsletter
104 -- 0Jason Cong, Wolfgang Rosenstiel. The Last Byte: The HLS tipping point

Volume 26, Issue 3

4 -- 0Erik Jan Marinissen, Yervant Zorian. Guest Editors Introduction: The Status of IEEE Std 1500 - Part 2
6 -- 15Krishna Chakravadhanula, Vivek Chickermane. Automating IEEE 1500 Core Test—An EDA Perspective
16 -- 24Alfredo Benso, Alberto Bosio, Stefano Di Carlo, Paolo Prinetto. Are IEEE-1500-Compliant Cores Really Compliant to the Standard?
25 -- 37Ozgur Sinanoglu, Erik Jan Marinissen, Anuja Sehgal, Jeff Fitzgerald, Jeff Rearick. Test Data Volume Comparison: Monolithic vs. Modular SoC Testing
38 -- 53Roberto Passerone, Imene Ben Hafaiedh, Susanne Graf, Albert Benveniste, Daniela Cancila, Arnaud Cuccuru, Sebastien Gerard, François Terrier, Werner Damm, Alberto Ferrari, Leonardo Mangeruca, Bernhard Josko, Thomas Peikenkamp, Alberto L. Sangiovanni-Vincentelli. Metamodels in Europe: Languages, Tools, and Applications
54 -- 69Alberto L. Sangiovanni-Vincentelli, Sandeep K. Shukla, Janos Sztipanovits, Guang Yang 0004, Deepak Mathaikutty. Metamodeling: An Emerging Representation Paradigm for System-Level Design
70 -- 77Ishwar Parulkar, Babu Turumella. Comprehensive Approach to High-Performance Server Chipset Debug
78 -- 86Vladimir A. Zivkovic, Jan Schat, Frank van der Heyden, Geert Seuren. Core-Based Testing of Embedded Mixed-Signal Modules in a SoC
87 -- 0Peggy Aycinena. DATE 2009 Workshop on 3D Integration
91 -- 0. DATC Newsletter
92 -- 93Scott Davidson. Book Review: A book on system test, and testing systems also
96 -- 0Sandeep K. Shukla. Metamodeling: What is it good for?

Volume 26, Issue 2

6 -- 7Yervant Zorian. Guest Editor s Introduction: Examples of Management Decision Criteria
8 -- 13Brad Beavers. The Story behind the Intel Atom Processor Success
14 -- 19Andrew Chang. Case Study of a 65-nm SoC Design
20 -- 29Jean-Pierre Schoellkopf, Philippe Magarshack. Low-Power Design Solutions forWireless Multimedia SoCs
30 -- 33Manuel d Abreu. From Specification to High-Volume Production
34 -- 43Kai-Hui Chang, David A. Papa, Igor L. Markov, Valeria Bertacco. Incremental Verification with Error Detection, Diagnosis, and Visualization
44 -- 51Wei Zhang. Computing and Minimizing Cache Vulnerability to Transient Errors
52 -- 63Andreas Apostolakis, Dimitris Gizopoulos, Mihalis Psarakis, Danilo Ravotto, Matteo Sonza Reorda. Test Program Generation for Communication Peripherals in Processor-Based SoC Devices
64 -- 73Li-Ming Denq, Yu-Tsao Hsing, Cheng-Wen Wu. Hybrid BIST Scheme for Multiple Heterogeneous Embedded Memories
76 -- 77Grant Martin. Processor Stew (review of Processor Description Languages by P. Mishra and N. Dutt, Eds.; 2008) [Book reviews]
84 -- 0Peggy Aycinena. Technical management: Best shaken, not stirred [The Last Byte]

Volume 26, Issue 1

6 -- 7Erik Jan Marinissen, Yervant Zorian. Guest Editors Introduction: The Status of IEEE Std 1500
8 -- 17Erik Jan Marinissen, Yervant Zorian. IEEE Std 1500 Enables Modular SoC Testing
18 -- 25Benoit Nadeau-Dostie, Saman Adham, Russ Abbott. Improved Core Isolation and Access for Hierarchical Embedded Test
26 -- 35Laung-Terng Wang, Ravi Apte, Shianling Wu, Boryau Sheu, Wen-Ben Jone, Jianghao Guo, Kuen-Jong Lee, Wei-Shin Wang, Xiaoqing Wen, Hao-Jan Chao, Jinsong Liu, Yanlong Niu, Yi-Chih Sung, Chi-Chun Wang, Fangfang Li. Turbo1500: Core-Based Design for Test and Diagnosis
36 -- 43Rohit Kapur, Paul Reuter, Sandeep Bhatia, Brion L. Keller. CTL and Its Usage in the EDA Industry
44 -- 51Teresa L. McLaurin, Stylianos Diamantidis, Irakis Diamantidis. The ARM Cortex-A8 Microprocessor IEEE Std 1500 Wrapper
52 -- 59Kedarnath J. Balakrishnan, Grady Giles, James Wingfield. Test Access Mechanism in the Quad-Core AMD Opteron Microprocessor
60 -- 67Lucia Costas-Perez, Juan J. Rodríguez-Andina. Algorithmic Concurrent Error Detection in Complex Digital-Processing Systems
68 -- 77Wenjing Rao, Alex Orailoglu, Ramesh Karri. Logic Mapping in Crossbar-Based Nanoarchitectures
78 -- 87Timothée Levi, Jean Tomas, Noëlle Lewis, Pascal Fouillat. A CMOS Resizing Methodology for Analog Circuits
88 -- 93Gadi Singer, Rajesh Galivanche, Srinivas Patil, Mike Tripp. The Challenges of Nanotechnology and Gigacomplexity
98 -- 101Scott Davidson. A second course on testing [review of System on Chip Test Architectures (Wang, L.-T et al., Eds.; 2007)]
104 -- 0Miron Abramovici, Al Crouch. We need more standards like IEEE 1500