| 6 | -- | 9 | Prabhat Mishra, Zeljko Zilic, Sandeep K. Shukla. Guest Editors Introduction: Multicore SoC Validation with Transaction-Level Models |
| 10 | -- | 19 | Samar Abdi, Yonghyun Hwang, Lochi Yu, Gunar Schirner, Daniel D. Gajski. Automatic TLM Generation for Early Validation of Multicore Systems |
| 20 | -- | 31 | Weiwei Chen, Xu Han, Rainer Dömer. Multicore Simulation of Transaction-Level Models Using the SoC Environment |
| 32 | -- | 43 | Frédéric Pétrot, Nicolas Fournel, Patrice Gerin, Marius Gligor, Mian Muhammed Hamayun, Hao Shen. On MPSoC Software Execution at the Transaction Level |
| 44 | -- | 51 | Bart Vermeulen, Kees Goossens. Interactive Debug of SoCs with Multiple Clocks |
| 52 | -- | 53 | Zeljko Zilic, Prabhat Mishra, Sandeep K. Shukla. Challenges of Rapidly Emerging Consumer Space Multiprocessors |
| 54 | -- | 63 | Ilia Polian, John P. Hayes. Selective Hardening: Toward Cost-Effective Error Tolerance |
| 64 | -- | 75 | Nathan Kupp, He Huang, Yiorgos Makris, Petros Drineas. Improving Analog and RF Device Yield through Performance Calibration |
| 76 | -- | 79 | Stan Krolikoski. Three Misconceptions Regarding Standards |
| 80 | -- | 81 | Scott Davidson. All About Liquid Scan Chains - and More [review of Digital Microfluidic Biochips: Design Automation and Optimization (Chakrabarty, K. and Xu, T.; 2010)] |
| 86 | -- | 89 | Andrew B. Kahng. The Future of Signoff |
| 96 | -- | 0 | Sandeep K. Shukla, Prabhat Mishra, Zeljko Zilic. A Brief History of Multiprocessors and EDA |