Journal: IEEE Design & Test of Computers

Volume 28, Issue 6

6 -- 0Jiun-Lang Huang, Kwang-Ting (Tim) Cheng. A Promising Alternative to Conventional Silicon
8 -- 15Tsung-Ching Huang, Jiun-Lang Huang, Kwang-Ting (Tim) Cheng. Robust Circuit Design for Flexible Electronics
16 -- 23William Wong, Tse Nga Ng, Sanjiv Sambandan, Michael Chabinyc. Materials, Processing, and Testing of Flexible Image Sensor Arrays
24 -- 31Chester Liu, En-Hua Ma, Wen-En Wei, Chien-Mo James Li, I-Chun Cheng, Yung-Hui Yeh. Placement Optimization of Flexible TFT Digital Circuits
32 -- 40Yindar Chuo, Badr Omrane, Clinton K. Landrock, Jeydmer Aristizabal, Donna Hohertz, Sasan Vosoogh-Grayli, Bozena Kaminska. Powering the Future: Organic Solar Cells with Polymer Energy Storage
41 -- 49Peter Maxwell. Adaptive Testing: Dealing with Process Variability
50 -- 57Youngsoo Shin, Seungwhun Paik. Pulsed-Latch Circuits: A New Dimension in ASIC Design
58 -- 65Kirk A. Gray, Michael Pecht. Long-Term Thermal Overstressing of Computers
66 -- 75Dallas Webster, Rick Hudgens, Donald Y. C. Lie. Replacing Error Vector Magnitude Test with RF and Analog BISTs
76 -- 84Louay Abdallah, Haralampos-G. D. Stratigopoulos, Salvador Mir, Christophe Kelma. RF Front-End Test Using Built-in Sensors
85 -- 87Bill Eklow. Major Milestones for Two IEEE Standards Groups in 2011
88 -- 89Andrew B. Kahng. Product Futures

Volume 28, Issue 5

4 -- 6Luciano Lavagno, Montek Singh. Guest Editors' Introduction: Asynchronous Design Is Here to Stay (and Is More Mainstream Than You Thought)
8 -- 22Steven M. Nowick, Montek Singh. High-Performance Asynchronous Pipelines: An Overview
23 -- 35Ran Ginosar. Metastability and Synchronizers: A Tutorial
36 -- 51Peter A. Beerel, Georgios D. Dimou, Andrew Lines. Proteus: An ASIC Flow for GHz Asynchronous Designs
52 -- 61Jo C. Ebergen, Daniel Finchelstein, Russell Kao, Jon K. Lexau, David Hopkins. An Evaluation of Asynchronous Stacks
62 -- 71Rafael Iankowski Soares, Ney Laert Vilar Calazans, Fernando Gehm Moraes, Philippe Maurine, Lionel Torres. A Robust Architectural Approach for Cryptographic Algorithms Using GALS Pipelines
72 -- 83Mariagrazia Graziano, Marco Vacca, Davide Blua, Maurizio Zamboni. Asynchrony in Quantum-Dot Cellular Automata Nanocomputation: Elixir or Poison?
84 -- 94Jean-Frédéric Christmann, Edith Beigné, Cyril Condemine, Pascal Vivet, Jérôme Willemin, Nicolas Leblond, Christian Piguet. Bringing Robustness and Power Efficiency to Autonomous Energy-Harvesting Microsystems
104 -- 106Andrew B. Kahng. Roadmapping Power
107 -- 109Stan Krolikoski. Explicit and Implicit Contributions to Standards Groups
110 -- 111Nicolas Troquard. Learning and Practice of the Property Specification Language
116 -- 0Al Davis. Asynchronous FUD

Volume 28, Issue 4

6 -- 7George A. Constantinides, Nicola Nicolici. Guest Editors' Introduction: Surveying the Landscape of FPGA Accelerator Research
8 -- 17George A. Constantinides, Adam B. Kinsman, Nicola Nicolici. Numerical Data Representations for FPGA-Based Scientific Computing
18 -- 27Florent de Dinechin, Bogdan Pasca. Designing Custom Arithmetic Data Paths with FloPoCo
28 -- 37Diego Sanchez-Roman, Gustavo Sutter, Sergio López-Buedo, Ivan Gonzalez, Francisco J. Gomez-Arribas, Javier Aracil, Francisco Palacios. High-Level Languages and Floating-Point Arithmetic for FPGA-Based CFD Simulations
38 -- 47Joonseok Park, Pedro C. Diniz. Data Reorganization and Prefetching of Pointer-Based Data Structures
48 -- 57Ming Liu, Zhonghai Lu, Wolfgang Kuehn, Axel Jantsch. FPGA-Based Particle Recognition in the HADES Experiment
58 -- 67Devi Yalamarthy, Joel Coburn, Rajesh Gupta, Glen Edwards, Mark Kelly. Computational Mass Spectrometry in a Reconfigurable Coherent Coprocessing Architecture
68 -- 77Greg Stitt, Alan D. George, Herman Lam, Melissa C. Smith, Vikas Aggarwal, Gongyu Wang, Casey Reardon, Brian Holland, Seth Koehler, James Coole. An End-to-End Tool Flow for FPGA-Accelerated Scientific Computing
78 -- 87Radu Marculescu, Paul Bogdan. Cyberphysical Systems: Workload Modeling and Design Optimization
88 -- 97Shyue-Kung Lu, Yin Chen, Shi-Yu Huang, Cheng Wu. Speeding Up Emulation-Based Diagnosis Techniques for Logic Cores
98 -- 101Igor L. Markov. Getting Your Bits in Order
112 -- 0Vaughn Betz. FPGAs, Programming Models, and Kit Cars

Volume 28, Issue 3

6 -- 9Prabhat Mishra, Zeljko Zilic, Sandeep K. Shukla. Guest Editors Introduction: Multicore SoC Validation with Transaction-Level Models
10 -- 19Samar Abdi, Yonghyun Hwang, Lochi Yu, Gunar Schirner, Daniel D. Gajski. Automatic TLM Generation for Early Validation of Multicore Systems
20 -- 31Weiwei Chen, Xu Han, Rainer Dömer. Multicore Simulation of Transaction-Level Models Using the SoC Environment
32 -- 43Frédéric Pétrot, Nicolas Fournel, Patrice Gerin, Marius Gligor, Mian Muhammed Hamayun, Hao Shen. On MPSoC Software Execution at the Transaction Level
44 -- 51Bart Vermeulen, Kees Goossens. Interactive Debug of SoCs with Multiple Clocks
52 -- 53Zeljko Zilic, Prabhat Mishra, Sandeep K. Shukla. Challenges of Rapidly Emerging Consumer Space Multiprocessors
54 -- 63Ilia Polian, John P. Hayes. Selective Hardening: Toward Cost-Effective Error Tolerance
64 -- 75Nathan Kupp, He Huang, Yiorgos Makris, Petros Drineas. Improving Analog and RF Device Yield through Performance Calibration
76 -- 79Stan Krolikoski. Three Misconceptions Regarding Standards
80 -- 81Scott Davidson. All About Liquid Scan Chains - and More [review of Digital Microfluidic Biochips: Design Automation and Optimization (Chakrabarty, K. and Xu, T.; 2010)]
86 -- 89Andrew B. Kahng. The Future of Signoff
96 -- 0Sandeep K. Shukla, Prabhat Mishra, Zeljko Zilic. A Brief History of Multiprocessors and EDA

Volume 28, Issue 2

6 -- 15Jason Cong, Glenn Reinman, A. Bui, V. Sarkar. Customizable Domain-Specific Computing
16 -- 29Luciano Ost, Guilherme Guindani, Fernando Gehm Moraes, Leandro Soares Indrusiak, Sanna Määttä. Exploring NoC-Based MPSoC Design Space with Power Estimation Models
30 -- 39Seung Eun Lee, Yoon Seok Yang, G. S. Choi, Wei Wu, Ravi R. Iyer. Low-Power, Resilient Interconnection with Orthogonal Latin Squares
40 -- 51Chin-Lung Chuang, Chien-Nan Jimmy Liu. Hybrid Testbench Acceleration for Reducing Communication Overhead
52 -- 61Mahmut Yilmaz, Mohammad Tehranipoor, Krishnendu Chakrabarty. A Metric to Target Small-Delay Defects in Industrial Circuits
62 -- 69Katherine Shu-Min Li, Jr-Yang Huang. Synthesizing Multiple Scan Trees to Optimize Test Application Time
70 -- 73Grant Martin. Will hardware and software be codesigned? [review of A Practical Introduction to Hardware/Software Codesign (Schaumont, P.R.; 2010)]
74 -- 75Andrew B. Kahng. Roads not taken

Volume 28, Issue 1

6 -- 8Chris H. Kim, Leland Chang. Guest editors introduction: Nanoscale Memories Pose Unique Challenges
10 -- 13Kiyoo Itoh. Embedded Memories: Progress and a Look into the Future
14 -- 21Darren Anand, Kevin Gorman, Mark Jacunski, Adrian Paparelli. Embedded DRAM in 45-nm Technology and Beyond
22 -- 31Fatih Hamzaoglu, Yih Wang, Pramod Kolar, Liqiong Wei, Yong-Gee Ng, Uddalak Bhattacharya, Kevin Zhang. Bit Cell Optimizations and Circuit Techniques for Nanoscale SRAM Design
32 -- 43Masood Qazi, Mahmut Sinangil, Anantha Chandrakasan. Challenges and Directions for Low-Voltage SRAM
44 -- 51Yuan Xie. Modeling, Architecture, and Applications for Emerging Memory Technologies
52 -- 63Takayuki Kawahara. Scalable Spin-Transfer Torque RAM Technology for Normally-Off Computing
64 -- 71Shyh-Shyuan Sheu, Kuo-Hsing Cheng, Meng-Fan Chang, Pei-Chia Chiang, Wen-Pin Lin, Heng-Yuan Lee, Pang-Shiu Chen, Yu-Sheng Chen, Frederick T. Chen, Ming-Jinn Tsai. Fast-Write Resistive RAM (RRAM) for Embedded Applications
76 -- 77Andrew B. Kahng. Design for manufacturability: Then and now
78 -- 79Igor L. Markov. EDA: Synergy or sum of the parts? [review of Electronic Design Automation: Synthesis, Verification and Test (Systems on Silicon (Wang, L.-T., Eds., et al; 2009)]