| 1 | -- | 3 | Ken S. Stevens, Sandeep K. Shukla, Montek Singh, Jean-Pierre Talpin. Preface |
| 5 | -- | 28 | Ankur Agiwal, Montek Singh. Multi-Clock Latency-Insensitive Architecture and Wrapper Synthesis |
| 29 | -- | 40 | David S. Bormann. GALS Test Chip on 130nm Process |
| 41 | -- | 59 | Julien Boucaron, Jean-Vivien Millo, Robert de Simone. Another Glance at Relay Stations in Latency-Insensitive Design |
| 61 | -- | 80 | Luca P. Carloni. The Role of Back-Pressure in Implementing Latency-Insensitive Systems |
| 81 | -- | 103 | Sohini Dasgupta, Dumitru Potop-Butucaru, Benoît Caillaud, Alexandre Yakovlev. Moving from Weakly Endochronous Systems to Delay-Insensitive Circuits |
| 105 | -- | 131 | Frederic Doucet, Massimiliano Menarini, Ingolf H. Krüger, Rajesh K. Gupta, Jean-Pierre Talpin. A Verification Approach for GALS Integration of Synchronous Components |
| 133 | -- | 149 | Frank K. Gürkaynak, Stephan Oetiker, Hubert Kaeslin, Norbert Felber, Wolfgang Fichtner. Design Challenges for a Differential-Power-Analysis Aware GALS-based AES Crypto ASIC |
| 151 | -- | 167 | Julien Ouy. A Survey of Desynchronization in a Polychronous Model of Computation |
| 169 | -- | 188 | Syed Suhaib, Deepak Mathaikutty, Sandeep K. Shukla, David Berner, Jean-Pierre Talpin. A Functional Programming Framework for Latency Insensitive Protocol Validation |
| 189 | -- | 206 | Xu Wang, Marta Z. Kwiatkowska, Georgios K. Theodoropoulos, Qianyi Zhang. Opportunities and Challenges in Process-algebraic Verification of Asynchronous Circuit Designs |